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* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-142-11/+14
| | | | | | cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
* Add an option to not print the alias of an instruction. It defaults to "printBill Wendling2011-04-131-2/+4
| | | | | | the alias". llvm-svn: 129485
* During post-legalization DAG combining, be careful to only create shifts ↵Owen Anderson2011-04-131-1/+8
| | | | | | where the RHS is of the legal type for the new operation. llvm-svn: 129484
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-6/+10
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Vectors with different number of elements of the same element type can haveMon P Wang2011-04-131-6/+64
| | | | | | | | the same allocation size but different primitive sizes(e.g., <3xi32> and <4xi32>). When ScalarRepl promotes them, it can't use a bit cast but should use a shuffle vector instead. llvm-svn: 129472
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-5/+11
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-132-8/+16
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich2011-04-131-1/+1
| | | | llvm-svn: 129468
* Fix a regression caused by r102515 where explicit alignment on globals isCameron Zwarich2011-04-131-1/+1
| | | | | | | ignored. There was a test to catch this, but it was just blindly updated in a large change. This fixes another part of <rdar://problem/9275290>. llvm-svn: 129466
* Fix debug message.Devang Patel2011-04-131-1/+3
| | | | llvm-svn: 129463
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-131-1/+33
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Remove extra bytes that were added for gdb. We do not have good poiner to ↵Devang Patel2011-04-131-8/+1
| | | | | | understand actual reason behind this fixme. Spot checking suggest that newer gdb does not need this. llvm-svn: 129461
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-3/+11
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Forgot to add this change for ↵Johnny Chen2011-04-131-4/+4
| | | | | | http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. llvm-svn: 129451
* Fixed the revision 129449.Junjie Gu2011-04-131-1/+1
| | | | llvm-svn: 129450
* Passing unroll parameters (unroll-count, threshold, and partial unroll) via ↵Junjie Gu2011-04-131-12/+23
| | | | | | | | | LoopUnroll class's ctor. Doing so will allow multiple context with different loop unroll parameters to run. This is a minor change and no effect on existing application. llvm-svn: 129449
* Add the alias analysis to the C api.Rafael Espindola2011-04-131-0/+9
| | | | llvm-svn: 129447
* MCJIT relocation resolution.Jim Grosbach2011-04-131-0/+2
| | | | llvm-svn: 129445
* PR9214: Convert ConstantExpr::getIndices() to return an ArrayRef, plusJay Foad2011-04-134-12/+10
| | | | | | related tweaks to ExprMapKeyType. llvm-svn: 129443
* Stop using dead function.Jakob Stoklund Olesen2011-04-133-18/+0
| | | | llvm-svn: 129442
* Remove some redundant llvm:: prefixes.Jay Foad2011-04-131-1/+1
| | | | llvm-svn: 129441
* PR9214: Convert ConstantExpr::getWithOperands() to use ArrayRef.Jay Foad2011-04-132-7/+6
| | | | llvm-svn: 129439
* Like the coding standards say, do not use "using namespace std".Jay Foad2011-04-131-2/+2
| | | | llvm-svn: 129435
* Fix an obvious problem with an alignment computation. AsmPrinter actually doesCameron Zwarich2011-04-131-1/+1
| | | | | | | the max itself, so it is not easy to write a test case for this, but I added a test case that would fail if the code in AsmPrinter were removed. llvm-svn: 129432
* Fix a typo.Cameron Zwarich2011-04-132-7/+7
| | | | llvm-svn: 129429
* If a global variable has a specified alignment that is less than the preferredCameron Zwarich2011-04-131-2/+6
| | | | | | | alignment for its type, use the minimum of the specified alignment and the ABI alignment. This fixes <rdar://problem/9275290>. llvm-svn: 129428
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-132-156/+190
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* Reapply r129401 with patch for clang.Bill Wendling2011-04-135-40/+30
| | | | llvm-svn: 129419
* Temporarily revert r129408 to see if it brings the bots back.Eric Christopher2011-04-131-0/+2
| | | | llvm-svn: 129417
* Be consistent about being virtual and returning void in the cfi methods.Rafael Espindola2011-04-123-73/+94
| | | | | | Implement the ones that were missing in the asm streamer. llvm-svn: 129413
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-121-0/+29
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* Add @earlyclobber constraints to the writeback register of all ARM store ↵Jakob Stoklund Olesen2011-04-122-12/+24
| | | | | | | | | | instructions. The ARMARM specifies these instructions as unpredictable when storing the writeback register. This shouldn't affect code generation much since storing a pointer to itself is quite rare. llvm-svn: 129409
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-121-2/+0
| | | | | | | | registers for fast allocation. Fixes rdar://9207598 llvm-svn: 129408
* I missed this new file in previous commit.Devang Patel2011-04-121-0/+973
| | | | llvm-svn: 129407
* Simplify. There is no need to use static variable.Devang Patel2011-04-121-3/+1
| | | | llvm-svn: 129406
* Do not reuse parameter name.Devang Patel2011-04-121-1/+1
| | | | llvm-svn: 129405
* Revert r129401 for now. Clang is using the old way of doing things.Bill Wendling2011-04-125-30/+40
| | | | llvm-svn: 129403
* This mechanical patch moves type handling into CompileUnit from DwarfDebug. ↵Devang Patel2011-04-124-1304/+377
| | | | | | In case of multiple compile unit in one object file, each compile unit is responsible for its own set of type entries anyway. This refactoring makes this obvious. llvm-svn: 129402
* Remove the unaligned load intrinsics in favor of using native unaligned loads.Bill Wendling2011-04-125-40/+30
| | | | | | | | | Now that we have a first-class way to represent unaligned loads, the unaligned load intrinsics are superfluous. First part of <rdar://problem/8460511>. llvm-svn: 129401
* Add more comments... err debug statements to the fast allocator.Eric Christopher2011-04-121-3/+16
| | | | llvm-svn: 129400
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-122-6/+11
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* SparseBitVector is SLOW.Jakob Stoklund Olesen2011-04-122-48/+58
| | | | | | | Use a Bitvector instead, we didn't need the smaller memory footprint anyway. This makes the greedy register allocator 10% faster. llvm-svn: 129390
* MCJIT lazy relocation resolution and symbol address re-assignment.Jim Grosbach2011-04-121-98/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add handling for tracking the relocations on symbols and resolving them. Keep track of the relocations even after they are resolved so that if the RuntimeDyld client moves the object, it can update the address and any relocations to that object will be updated. For our trival object file load/run test harness (llvm-rtdyld), this enables relocations between functions located in the same object module. It should be trivially extendable to load multiple objects with mutual references. As a simple example, the following now works (running on x86_64 Darwin 10.6): $ cat t.c int bar() { return 65; } int main() { return bar(); } $ clang t.c -fno-asynchronous-unwind-tables -o t.o -c $ otool -vt t.o t.o: (__TEXT,__text) section _bar: 0000000000000000 pushq %rbp 0000000000000001 movq %rsp,%rbp 0000000000000004 movl $0x00000041,%eax 0000000000000009 popq %rbp 000000000000000a ret 000000000000000b nopl 0x00(%rax,%rax) _main: 0000000000000010 pushq %rbp 0000000000000011 movq %rsp,%rbp 0000000000000014 subq $0x10,%rsp 0000000000000018 movl $0x00000000,0xfc(%rbp) 000000000000001f callq 0x00000024 0000000000000024 addq $0x10,%rsp 0000000000000028 popq %rbp 0000000000000029 ret $ llvm-rtdyld t.o -debug-only=dyld ; echo $? Function sym: '_bar' @ 0 Function sym: '_main' @ 16 Extracting function: _bar from [0, 15] allocated to 0x100153000 Extracting function: _main from [16, 41] allocated to 0x100154000 Relocation at '_main' + 16 from '_bar(Word1: 0x2d000000) Resolving relocation at '_main' + 16 (0x100154010) from '_bar (0x100153000)(pcrel, type: 2, Size: 4). loaded '_main' at: 0x100154000 65 $ llvm-svn: 129388
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+45
| | | | | | rdar://problem/9269047 llvm-svn: 129387
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-122-184/+157
| | | | llvm-svn: 129385
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-122-157/+184
| | | | | | | | | | | | UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make these heuristic adjustments to node latency work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129383
* Create new intervals for isolated blocks during region splitting.Jakob Stoklund Olesen2011-04-123-37/+46
| | | | | | | | | This merges the behavior of splitSingleBlocks into splitAroundRegion, so the RS_Region and RS_Block register stages can be coalesced. That means the leftover intervals after region splitting go directly to spilling instead of a second pass of per-block splitting. llvm-svn: 129379
* Remove LastOffset from the asm parser.Rafael Espindola2011-04-123-21/+20
| | | | llvm-svn: 129378
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-122-0/+5
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Add SplitKit API to query and select the current interval being worked on.Jakob Stoklund Olesen2011-04-122-2/+17
| | | | | | This makes it possible to target multiple registers in one pass. llvm-svn: 129374
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