| Commit message (Collapse) | Author | Age | Files | Lines |
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when using structured exception handling (SEH) on Windows 64.
http://llvm-reviews.chandlerc.com/D2378
Patch by Jonathan Liu!
llvm-svn: 197483
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Bader).
Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.
llvm-svn: 197482
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This reverts commit r197469.
The sanitizer and dragonegg buildbots are failing, I think because of
this change. Reverting until I figure out why.
llvm-svn: 197481
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The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS. Mark it so, or else the scheduler might
place it in the middle of another test+branch.
This fixes a bug exposed by r192750, which turned on the MI Scheduler
for X86.
<rdar://problem/15627766>
llvm-svn: 197469
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coalesces normal copies.
Without this, MachineCSE is powerless to handle redundant operations with truncated source operands.
This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled:
%vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
%vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
%vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>
Test case: cse-add-with-overflow.ll.
This exposed an existing bug in
PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case:
PowerPC/crash.ll.
llvm-svn: 197465
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llvm-svn: 197464
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Re-reading the comment I updated in previous commit, it's better to make
it more explicit and avoid ambiguity more effectively.
llvm-svn: 197458
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llvm-svn: 197457
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Make debugging ISel a bit easier by printing out a dump of the generated
code at the end.
llvm-svn: 197456
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dependency at link time
llvm-svn: 197451
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A phi node operand or an instruction operand could be a constant expression that
can trap (division). Check that we don't vectorize such cases.
PR16729
radar://15653590
llvm-svn: 197449
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DiagnosticPrinter.cpp.
These was creating a link time dependencies of IR on CodeGen and Analysis.
Part of <rdar://problem/15515174>
llvm-svn: 197447
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The patch adds a new LLVMContext::diagnose that can be used to communicate to
the front-end, if any, that something of interest happened.
The diagnostics are supported by a new abstraction, the DiagnosticInfo class.
The base class contains the following information:
- The kind of the report: What this is about.
- The severity of the report: How bad this is.
This patch also adds 2 classes:
- DiagnosticInfoInlineAsm: For inline asm reporting. Basically, this diagnostic
will be used to switch to the new diagnostic API for LLVMContext::emitError.
- DiagnosticStackSize: For stack size reporting. Comes as a replacement of the
hard coded warning in PEI.
This patch also features dynamic diagnostic identifiers. In other words plugins
can use this infrastructure for their own diagnostics (for more details, see
getNextAvailablePluginDiagnosticKind).
This patch introduces a new DiagnosticHandlerTy and a new DiagnosticContext in
the LLVMContext that should be set by the front-end to be able to map these
diagnostics in its own system.
http://llvm-reviews.chandlerc.com/D2376
<rdar://problem/15515174>
llvm-svn: 197438
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'fmin/fmax'. Fix radar:15283121
llvm-svn: 197434
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Outputs branch information for unconditional branches in addition to
conditional branches. -b option must be enabled.
Also updated tests.
llvm-svn: 197432
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aligned arguments.
This allows the WebKit_JS calling convention to perform partial writes on a 4
byte granularity to stack slots.
llvm-svn: 197431
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SI_KIL -> SI_KILL
llvm-svn: 197425
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that it coalesces normal copies."
This reverts commit r197414.
It broke the ppc64 bootstrap. I will post a testcase in a sec.
llvm-svn: 197424
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llvm-svn: 197418
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WebKit_JS calling convention.
Pass the first integer argument (callee) in register to optimize inline caches.
llvm-svn: 197416
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that it coalesces normal copies.
Without this, MachineCSE is powerless to handle redundant operations
with truncated source operands.
This required fixing the 2-addr pass to handle tied subregisters. It
isn't clear what combinations of subregisters can legally be tied, but
the simple case of truncated source operands is now safely handled:
%vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
%vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
%vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>
llvm-svn: 197414
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llvm-svn: 197413
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Produce them in the same order on every target. The order is that of
getStringRepresentation: e|E-i*-f*-v*-a*-s*-n*-S*.
llvm-svn: 197411
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While there, simplify "p3:32:32:32" to "p3:32:32".
llvm-svn: 197407
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llvm-svn: 197405
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Floating-point Compare to Zero.
llvm-svn: 197402
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This was manifesting as an LLVM_ASSUME_ALIGNED() failure in an ELF debug
info test when building LLVM with clang in the Microsoft C++ ABI.
llvm-svn: 197401
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llvm-svn: 197400
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llvm-svn: 197398
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llvm-svn: 197397
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PowerPC now has an asm parser (and has for many months now); indicate this in
PowerPC/LLVMBuild.txt.
llvm-svn: 197393
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Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
llvm-svn: 197384
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llvm-svn: 197366
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Currently we have such types as legal vector types. The DAG combiner may generate some DAG nodes having such types but we don't have patterns to match them.
E.g. a load i32 and a bitcast i32 to v1i32 will be combined into a load v1i32:
bitcast (load i32) to v1i32 -> load v1i32.
So this patch fixes such problems for load/dup instructions.
If v1i8/v1i16/v1i32 are not legal any more, the code in this patch can be deleted. So I also add some FIXME.
llvm-svn: 197361
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that follows).
llvm-svn: 197358
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llvm-svn: 197357
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part of a multi-line pseudo which worked around a linker bug for mips16.
llvm-svn: 197356
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Some tiny cosmetic code changes to follow. Because of the wide
ranging nature of the patch a full 24 test cycle was needed to
check against regression. This was the smallest patch I could
make to progress from the earlier ones in the series.
llvm-svn: 197350
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llvm-svn: 197348
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llvm-svn: 197335
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llvm-svn: 197332
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llvm-svn: 197329
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llvm-svn: 197327
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This is a base implementation of the powerpc-apple-darwin asm parser dialect.
* Enables infrastructure (essentially isDarwin()) and fixes up the parsing of asm directives to separate out ELF and MachO/Darwin additions.
* Enables parsing of {r,f,v}XX as register identifiers.
* Enables parsing of lo16() hi16() and ha16() as modifiers.
The changes to the test case are from David Fang (fangism).
llvm-svn: 197324
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llvm-svn: 197323
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This optional register liveness analysis pass can be enabled with either
-enable-stackmap-liveness, -enable-patchpoint-liveness, or both. The pass
traverses each basic block in a machine function. For each basic block the
instructions are processed in reversed order and if a patchpoint or stackmap
instruction is encountered the current live-out register set is encoded as a
register mask and attached to the instruction.
Later on during stackmap generation the live-out register mask is processed and
also emitted as part of the stackmap.
This information is optional and intended for optimization purposes only. This
will enable a client of the stackmap to reason about the registers it can use
and which registers need to be preserved.
Reviewed by Andy
llvm-svn: 197317
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llvm-svn: 197316
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of just register units.
Reviewed by Andy
llvm-svn: 197315
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No functionality change.
llvm-svn: 197312
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No functionality change.
llvm-svn: 197311
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