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* [LAA] Lift RuntimePointerCheck out of LoopAccessInfo, NFCAdam Nemet2015-07-144-55/+53
| | | | | | | | | I am planning to add more nested classes inside RuntimePointerCheck so all these triple-nesting would be hard to follow. Also rename it to RuntimePointerChecking (i.e. append 'ing'). llvm-svn: 242218
* [PowerPC] Use the ABI indirect-call protocol for patchpointsHal Finkel2015-07-141-1/+43
| | | | | | | | | | | | We used to take the address specified as the direct target of the patchpoint and did no TOC-pointer handling. This, however, as not all that useful, because MCJIT tends to create a lot of modules, and they have their own TOC sections. Thus, to call from the generated code to other generated code, you really need to switch TOC pointers. Make this work as expected, and under ELFv1, tread the address as the function descriptor address so that the correct TOC pointer can be loaded. llvm-svn: 242217
* Add support for reading members out of thin archives.Rafael Espindola2015-07-141-1/+22
| | | | | | | | | | For now the Archive owns the buffers of the thin archive members. This makes for a simple API, but all the buffers are destructed only when the archive is destructed. This should be fine since we close the files after mmap so we should not hit an open file limit. llvm-svn: 242215
* Add allnodes() iterator range to SelectionDAG. NFC.Pete Cooper2015-07-144-20/+12
| | | | | | | | | | | SelectionDAG already had begin/end methods for iterating over all the nodes, but didn't define an iterator_range for us in foreach loops. This adds such a method and uses it in some of the eligible places throughout the backends. llvm-svn: 242212
* Constify parameters in SelectionDAG methods. NFCPete Cooper2015-07-141-3/+3
| | | | llvm-svn: 242210
* Remove unnecessary .getNode() in SelectionDAG. NFC.Pete Cooper2015-07-141-22/+20
| | | | | | | | The simplify_type specialisation allows us to cast directly from SDValue to an SDNode* subclass so we don't need to pass a SDNode* to cast<>. llvm-svn: 242209
* Use more foreach loops in SelectionDAG. NFCPete Cooper2015-07-141-7/+6
| | | | llvm-svn: 242208
* MIR Serialization: Serialize the machine basic block live in registers.Alex Lorenz2015-07-144-1/+44
| | | | llvm-svn: 242204
* MIR Printer: move the function 'printReg'. NFC.Alex Lorenz2015-07-141-13/+13
| | | | | | | | This commit moves the function 'printReg' towards the start of the file so that it can be used by the conversion methods in MIRPrinter and not just the printing methods in MIPrinter. llvm-svn: 242203
* GVN: use a static array instead of regenerating it each time. NFC.Tim Northover2015-07-141-1/+1
| | | | llvm-svn: 242202
* WebAssembly: add basic int/fp instruction codegen.JF Bastien2015-07-143-28/+63
| | | | | | | | | | | | Summary: This patch has the most basic instruction codegen for 32 and 64 bit int/fp. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11193 llvm-svn: 242201
* Fix NDEBUG build warningKrzysztof Parzyszek2015-07-141-0/+2
| | | | llvm-svn: 242200
* GVN: tolerate an instruction being replaced without existing in the leaderboardTim Northover2015-07-141-1/+4
| | | | | | | | | | | | | | Sometimes an incidentally created instruction can duplicate a Value used elsewhere. It then often doesn't end up in the leader table. If it's later removed, we attempt to remove it from the leader table and segfault. Instead we should just ignore the removal request, which won't cause any problems. The reverse situation, where the original instruction is replaced by the new one (which you might think could leave the leader table empty) cannot occur, because the incidental instruction will never be found in the first place. llvm-svn: 242199
* Fix Windows build: replace __func__ with LLVM_FUNCTION_NAMEKrzysztof Parzyszek2015-07-141-4/+5
| | | | llvm-svn: 242192
* [MMX] Use the appropriate instructions for GR64 <-> VR64 copies.Bruno Cardoso Lopes2015-07-141-2/+2
| | | | | | | | | | | | | | | MOVSDto64rr and MOV64toSDrr are defined to convert between FR64 (%xmm) <-> GR64 registers, not VR64 (%mm) <-> GR64. This is wrong. I found this by inspection and could not find a suitable testcase for it since (1) we don't handle MMX bitcasts in Peephole optimizer as to generate COPYs that (2) could be expanded back to the appropriate x86 instruction in ExpandPostRA. Switch to use the appropriate instructions: MMX_MOVD64from64rr and MMX_MOVD64to64rr here. llvm-svn: 242191
* [PowerPC] Fix the PPCInstrInfo::getInstrLatency implementationHal Finkel2015-07-145-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PowerPC uses itineraries to describe processor pipelines (and dispatch-group restrictions for P7/P8 cores). Unfortunately, the target-independent implementation of TII.getInstrLatency calls ItinData->getStageLatency, and that looks for the largest cycle count in the pipeline for any given instruction. This, however, yields the wrong answer for the PPC itineraries, because we don't encode the full pipeline. Because the functional units are fully pipelined, we only model the initial stages (there are no relevant hazards in the later stages to model), and so the technique employed by getStageLatency does not really work. Instead, we should take the maximum output operand latency, and that's what PPCInstrInfo::getInstrLatency now does. This caused some test-case churn, including two unfortunate side effects. First, the new arrangement of copies we get from function parameters now sometimes blocks VSX FMA mutation (a FIXME has been added to the code and the test cases), and we have one significant test-suite regression: SingleSource/Benchmarks/BenchmarkGame/spectral-norm 56.4185% +/- 18.9398% In this benchmark we have a loop with a vectorized FP divide, and it with the new scheduling both divides end up in the same dispatch group (which in this case seems to cause a problem, although why is not exactly clear). The grouping structure is hard to predict from the bottom of the loop, and there may not be much we can do to fix this. Very few other test-suite performance effects were really significant, but almost all weakly favor this change. However, in light of the issues highlighted above, I've left the old behavior available via a command-line flag. llvm-svn: 242188
* [Hexagon] Generate instructions for operations on predicate registersKrzysztof Parzyszek2015-07-143-0/+531
| | | | | | | Convert logical operations on general-purpose registers to the correspon- ding operations on predicate registers. llvm-svn: 242186
* [CodeGen] Force emission of personality directive if explicitly specifiedKeno Fischer2015-07-145-22/+57
| | | | | | | | | | | | | | | | | | | Summary: Before this change, personality directives were not emitted if there was no invoke left in the function (of course until recently this also meant that we couldn't know what the personality actually was). This patch forces personality directives to still be emitted, unless it is known to be a noop in the absence of invokes, or the user explicitly specified `nounwind` (and not `uwtable`) on the function. Reviewers: majnemer, rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D10884 llvm-svn: 242185
* AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)Matt Arsenault2015-07-142-0/+35
| | | | | | | | | | | | | | | | | This can be done only with moves which theoretically will optimize better later. Although this transform increases the instruction count, it should be code size / cycle count neutral in the worst VALU case. It also seems to slightly improve a couple of testcases due to other DAG combines this exposes. This is probably slightly worse for the SALU case, so it might be better to handle this during moveToVALU, although then you lose some simplifications like the load width reducing in the simple testcase. llvm-svn: 242177
* AMDGPU/SI: Fix read2 merging into a super register.Matt Arsenault2015-07-143-13/+35
| | | | | | | | | | | | | | | | If the read2 produced was supposed to be writing into a super register, it would use the wrong subregister indices. Fix this by inserting copies, so we only ever write to a vreg_64. Run the register coalescer again to clean this up, although this isn't ideal and often does result in an extra move. Also remove the assert that offset1 > offset0. There isn't a real reason to not allow this other than a minor convenience in the compiler, and it doesn't seem worth the effort of avoiding it. llvm-svn: 242174
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-1416-122/+23
| | | | | | | | | | | | | We have a detailed def/use lists for every physical register in MachineRegisterInfo anyway, so there is little use in maintaining an additional bitset of which ones are used. Removing it frees us from extra book keeping. This simplifies VirtRegMap. Differential Revision: http://reviews.llvm.org/D10911 llvm-svn: 242173
* RAGreedy: Keep track of allocated PhysRegs internallyMatthias Braun2015-07-142-18/+32
| | | | | | | | | | | Do not use MachineRegisterInfo::setPhysRegUsed()/isPhysRegUsed() anymore. This bitset changes function-global state and is set by the VirtRegRewriter anyway. Simply use a bitvector private to RAGreedy. Differential Revision: http://reviews.llvm.org/D10910 llvm-svn: 242169
* Add missing builtins to the PPC back end for ABI compliance (vol. 4)Nemanja Ivanovic2015-07-141-0/+6
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D11183 Back end portion of the fourth round of additions to altivec.h. llvm-svn: 242167
* PrologEpilogInserter: Rewrite API to determine callee save regsiters.Matthias Braun2015-07-1426-134/+223
| | | | | | | | | | | | | | | | This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan(): - Rename the function to determineCalleeSaves() - Pass a bitset of callee saved registers by reference, thus avoiding the function-global PhysRegUsed bitset in MachineRegisterInfo. - Without PhysRegUsed the implementation is fine tuned to not save physcial registers which are only read but never modified. Related to rdar://21539507 Differential Revision: http://reviews.llvm.org/D10909 llvm-svn: 242165
* AArch64: add rev64 alias for 64-bit rev instruction.Tim Northover2015-07-141-0/+2
| | | | | | | It could be useful to assembly programmers and makes the permitted variants a little more uniform. llvm-svn: 242164
* [Hexagon] Generate "extract" instructions more aggressivelyKrzysztof Parzyszek2015-07-143-13/+278
| | | | | | | Generate extract instructions (via intrinsics) before the DAG combiner folds shifts into unrecognizable forms. llvm-svn: 242163
* ARMAsmParser: Take MCInst param by const-refHans Wennborg2015-07-141-8/+9
| | | | | | (Broken out from http://reviews.llvm.org/D11167) llvm-svn: 242160
* Caused regressions: compile Release+Asserts failed on clang-native-arm-cortex-a9Alexandros Lamprineas2015-07-141-96/+83
| | | | | | | | Revert "-Added API for retrieving the default FPU of a CPU from TargetParser." This reverts commit 01199ab0c6ff2d5c4f6b2c05a95ec011e41c4669. llvm-svn: 242147
* AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructionsTom Stellard2015-07-141-6/+27
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11061 llvm-svn: 242146
* Silencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to ↵Aaron Ballman2015-07-141-1/+1
| | | | | | 'int16_t' and truncation of constant value. NFC intended. llvm-svn: 242145
* -Added API for retrieving the default FPU of a CPU from TargetParser.Alexandros Lamprineas2015-07-141-83/+96
| | | | | | | | -Implemented as a table lookup. Change-Id: Ibf7217f6bd2769e9c06835a5aede3d072dee6757 Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242141
* [mips] Fix li/la differences between IAS and GAS.Daniel Sanders2015-07-141-82/+83
| | | | | | | | | | | | | | | | | | | Summary: - Signed 16-bit should have priority over unsigned. - For la, unsigned 16-bit must use ori+addu rather than directly use ori. - Correct tests on 32-bit immediates with 64-bit predicates by sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000) should be true and use addiu. Also split li/la testing into separate files due to their size. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10967 llvm-svn: 242139
* [PM/AA] Reformat GlobalsModRef so that subsequent patches I make hereChandler Carruth2015-07-141-155/+160
| | | | | | don't continually introduce formatting deltas. NFC llvm-svn: 242129
* [SROA] Don't de-atomic volatile loads and storesDavid Majnemer2015-07-141-6/+15
| | | | | | | | | | | Volatile loads and stores are made visible in global state regardless of what memory is involved. It is not correct to disregard the ordering and synchronization scope because it is possible to synchronize with memory operations performed by hardware. This partially addresses PR23737. llvm-svn: 242126
* Generate correct asm info for mingw and cygwin ARM targets.Yaron Keren2015-07-141-2/+2
| | | | | | | | | http://reviews.llvm.org/D11075 Patch by Martell Malone Reviewed by Reid Kleckner llvm-svn: 242123
* Prune trailing whitespaces and CRs.NAKAMURA Takumi2015-07-141-23/+23
| | | | llvm-svn: 242117
* Revert "LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization"Matthias Braun2015-07-141-150/+74
| | | | | | | | Accidental commit, needs review first. This reverts commit r242107. llvm-svn: 242108
* LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalizationMatthias Braun2015-07-141-74/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Factor out code to query and modify the sign bit of a floatingpoint value as an integer. This also works if none of the targets integer types is big enough to hold all bits of the floatingpoint value. - Legalize FABS(x) as FCOPYSIGN(x, 0.0) if FCOPYSIGN is available, otherwise perform bit manipulation on the sign bit. The previous code used "x >u 0 ? x : -x" which is incorrect for x being -0.0! It also takes 34 instructions on ARM Cortex-M4. With this patch we only require 5: vldr d0, LCPI0_0 vmov r2, r3, d0 lsrs r2, r3, #31 bfi r1, r2, #31, #1 bx lr (This could be further improved if the compiler would recognize that r2, r3 is zero). - Only lower FCOPYSIGN(x, y) = sign(x) ? -FABS(x) : FABS(x) if FABS is available otherwise perform bit manipulation on the sign bit. - Perform the sign(x) test by masking out the sign bit and comparing with 0 rather than shifting the sign bit to the highest position and testing for "<s 0". For x86 copysignl (on 80bit values) this gets us: testl $32768, %eax rather than: shlq $48, %rax sets %al testb %al, %al llvm-svn: 242107
* Add capability to get and set the personalitty function from the C APIAndrew Wilkins2015-07-141-0/+8
| | | | | | | | | | | | | | | Summary: The capability was lost with D10429 where the personality function was set at function level rather than landing pad level. Now there is no way to get/set the personality function from the C API. That is a problem. Note that the whole thing could be avoided by improving the C API testing, as started by D10725 Reviewers: chandlerc, bogner, majnemer, andrew.w.kaylor, rafael, rnk, axw Subscribers: rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D10946 llvm-svn: 242104
* Add a herper function. NFC.Rafael Espindola2015-07-141-8/+7
| | | | llvm-svn: 242100
* MIR Serialization: Serialize the variable sized stack objects.Alex Lorenz2015-07-142-4/+11
| | | | llvm-svn: 242095
* Update enforceKnownAlignment after the isWeakForLinker semantic changeReid Kleckner2015-07-141-7/+4
| | | | | | | | | | | | | Previously we would refrain from attempting to increase the linkage of available_externally globals because they were considered weak for the linker. Now they are treated more like a declaration instead of a weak definition. This was causing SSE alignment faults in Chromuim, when some code assumed it could increase the alignment of a dllimported global that it didn't control. http://crbug.com/509256 llvm-svn: 242091
* MIR Serialization: Serialize the sub register indices.Alex Lorenz2015-07-134-3/+53
| | | | | | | | This commit serializes the sub register indices from the register machine operands. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242084
* Fix reading archive members with / in the name.Rafael Espindola2015-07-131-3/+3
| | | | | | This is important for thin archives. llvm-svn: 242082
* [PPC64LE] More improvements to VSX swap optimizationBill Schmidt2015-07-131-21/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows VSX swap optimization to succeed more frequently. Specifically, it is concerned with common code sequences that occur when copying a scalar floating-point value to a vector register. This patch currently handles cases where the floating-point value is already in a register, but does not yet handle loads (such as via an LXSDX scalar floating-point VSX load). That will be dealt with later. A typical case is when a scalar value comes in as a floating-point parameter. The value is copied into a virtual VSFRC register, and then a sequence of SUBREG_TO_REG and/or COPY operations will convert it to a full vector register of the class required by the context. If this vector register is then used as part of a lane-permuted computation, the original scalar value will be in the wrong lane. We can fix this by adding a swap operation following any widening SUBREG_TO_REG operation. Additional COPY operations may be needed around the swap operation in order to keep register assignment happy, but these are pro forma operations that will be removed by coalescing. If a scalar value is otherwise directly referenced in a computation (such as by one of the many XS* vector-scalar operations), we currently disable swap optimization. These operations are lane-sensitive by definition. A MentionsPartialVR flag is added for use in each swap table entry that mentions a scalar floating-point register without having special handling defined. A common idiom for PPC64LE is to convert a double-precision scalar to a vector by performing a splat operation. This ensures that the value can be referenced as V[0], as it would be for big endian, whereas just converting the scalar to a vector with a SUBREG_TO_REG operation leaves this value only in V[1]. A doubleword splat operation is one form of an XXPERMDI instruction, which takes one doubleword from a first operand and another doubleword from a second operand, with a two-bit selector operand indicating which doublewords are chosen. In the general case, an XXPERMDI can be permitted in a lane-swapped region provided that it is properly transformed to select the corresponding swapped values. This transformation is to reverse the order of the two input operands, and to reverse and complement the bits of the selector operand (derivation left as an exercise to the reader ;). A new test case that exercises the scalar-to-vector and generalized XXPERMDI transformations is added as CodeGen/PowerPC/swaps-le-5.ll. The patch also requires a change to CodeGen/PowerPC/swaps-le-3.ll to use CHECK-DAG instead of CHECK for two independent instructions that now appear in reverse order. There are two small unrelated changes that are added with this patch. First, the XXSLDWI instruction was incorrectly omitted from the list of lane-sensitive instructions; this is now fixed. Second, I observed that the same webs were being rejected over and over again for different reasons. Since it's sufficient to reject a web only once, I added a check for this to speed up the compilation time slightly. llvm-svn: 242081
* Loop idiom recognizer was replacing too many uses of popcount.Pete Cooper2015-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When spotting that a loop can use ctpop, we were incorrectly replacing all uses of a value with a value derived from ctpop. The bug here was exposed because we were replacing a use prior to the ctpop with the ctpop value and so we have a use before def, i.e., we changed %tobool.5 = icmp ne i32 %num, 0 store i1 %tobool.5, i1* %ptr br i1 %tobool.5, label %for.body.lr.ph, label %for.end to store i1 %1, i1* %ptr %0 = call i32 @llvm.ctpop.i32(i32 %num) %1 = icmp ne i32 %0, 0 br i1 %1, label %for.body.lr.ph, label %for.end Even if we inserted the ctpop so that it dominates the store here, that would still be incorrect. The store doesn’t want the result of ctpop. The fix is very simple, and involves replacing only the branch condition with the ctpop instead of all uses. Reviewed by Hal Finkel. llvm-svn: 242068
* [WinEH] Emit the LSDA even if no lpads remain but outlining occurredReid Kleckner2015-07-131-6/+14
| | | | | | | | | | | | | | | The outlined funclets call intrinsics which reference labels from the LSDA. This situation can easily arise in small functions with a single cleanup at -O0, where Clang marks a definition as nounwind, and then WinEHPrepare "discovers" that the landingpad is dead by accident and deletes it. We now need to ask the LLVM IR Function for it's personality directly, rather than going through MachineModuleInfo. Fixes PR23892. llvm-svn: 242063
* [Hexagon] Move BitTracker into the llvm namespace and remove redundant ↵Benjamin Kramer2015-07-134-64/+52
| | | | | | | | qualifications No functional change intended. llvm-svn: 242062
* Add support deterministic output in llvm-ar and make it the default.Rafael Espindola2015-07-132-18/+45
| | | | llvm-svn: 242061
* AMDGPU: Minor cleanups to always inline passMatt Arsenault2015-07-131-7/+4
| | | | llvm-svn: 242053
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