summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [DAGCombine] Don't combine sext with extload if sextload is not supported ↵Guozhi Wei2017-10-271-1/+5
| | | | | | | | | | | | | | | and extload has multi users In function DAGCombiner::visitSIGN_EXTEND_INREG, sext can be combined with extload even if sextload is not supported by target, then if sext is the only user of extload, there is no big difference, no harm no benefit. if extload has more than one user, the combined sextload may block extload from combining with other zext, causes extra zext instructions generated. As demonstrated by the attached test case. This patch add the constraint that when sextload is not supported by target, sext can only be combined with extload if it is the only user of extload. Differential Revision: https://reviews.llvm.org/D39108 llvm-svn: 316802
* Make 32-bit member offset in Archive::Symbol::getMember 64-bitJake Ehrlich2017-10-271-1/+1
| | | | | | | | | | | | When accessing a member for a symbol with an offset greater than 2^32 - 1 the current Archive::Symbol::getMember implementation will overflow and cause unexpected behavior. This change simply fixes that. In particular if you call "llvm-nm --print-armap" on an archive that has this behavior you'll get an error. Differential Revision: https://reviews.llvm.org/D39379 llvm-svn: 316801
* Handle undefined weak hidden symbols on all architectures.Rafael Espindola2017-10-272-20/+12
| | | | | | | | | | | | | | | | We were handling the non-hidden case in lib/Target/TargetMachine.cpp, but the hidden case was handled in architecture dependent code and only X86_64 and AArch64 were covered. While it is true that some code sequences in some ABIs might be able to produce the correct value at runtime, that doesn't seem to be the common case. I left the AArch64 code in place since it also forces a got access for non-pic code. It is not clear if that is needed, but it is probably better to change that in another commit. llvm-svn: 316799
* Force #define GTEST_LANG_CXX11.Zachary Turner2017-10-271-0/+3
| | | | | | | | | | | | | | | | | | gtest depends on this #define to determine whether it can use various classes like std::tuple, or whether it has to fall back to experimental classes in the std::tr1 namespace. The check in the current version of gtest relies on the value of the `__cplusplus` macro, but MSVC provides a non-conformant value of this macro, making it effectively impossible to detect C++11. In short, LLVM compiled with MSVC has been silently using the tr1 versions of several classes since the beginning of time. This would normally be pretty benign, except that in the latest preview of MSVC they have marked all of the tr1 classes deprecated, so it spews thousands of warnings. llvm-svn: 316798
* [X86] Remove fast-isel code for handling i8 shifts. This is handled by auto ↵Craig Topper2017-10-271-14/+7
| | | | | | generated code. llvm-svn: 316797
* Improve clamp recognition in ValueTracking.Artur Gainullin2017-10-271-12/+26
| | | | | | | | | | | | | | | | Summary: ValueTracking was recognizing not all variations of clamp. Swapping of true value and false value of select was added to fix this problem. The first patch was reverted because it caused miscompile in NVPTX target. Added corresponding test cases. Reviewers: spatel, majnemer, efriedma, reames Subscribers: llvm-commits, jholewinski Differential Revision: https://reviews.llvm.org/D39240 llvm-svn: 316795
* [X86] Teach fastisel to use VLX VMOVNTDQA for v4f64 and 256-bit integers ↵Craig Topper2017-10-271-2/+2
| | | | | | | | when available. This looks to have been missed from r280682. llvm-svn: 316790
* Fix llvm-special-case-list-fuzzer regexp exceptionVlad Tsyrklevich2017-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Original oss-fuzz report: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3727#c2 The minimized test case that causes this failure: 5b 5b 5b 3d 47 53 00 5b 3d 5d 5b 5d 0a [[[=GS.[=][]. Note the string "=GS\x00". The failure happens because the code is searching the string against an array of known collated names. "GS\x00" is a hit, but since len takes into account an extra NUL byte, indexing into cp->name[len] goes one byte past it's allocated memory. Fix this to use a strlen(cp->name) comparison to account for NUL bytes in the input. Reviewers: pcc Reviewed By: pcc Subscribers: hctim, kcc Differential Revision: https://reviews.llvm.org/D39380 llvm-svn: 316786
* [Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cppKrzysztof Parzyszek2017-10-271-1/+1
| | | | | | | Making sure that an instruction has fewer operands than required, then attempting to access one out of range is going to fail. llvm-svn: 316785
* ELF: Add support for emitting dynamic relocations in the Android relocation ↵Peter Collingbourne2017-10-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | packing format. The Android relocation packing format is a more compact format for dynamic relocations in executables and DSOs that is based on delta encoding and SLEBs. An overview of the format can be found in the Android source code: https://android.googlesource.com/platform/bionic/+/refs/heads/master/tools/relocation_packer/src/delta_encoder.h This patch implements relocation packing using that format. This implementation uses a more intelligent algorithm for compressing relative relocations than Android's own relocation packer. As a result it can generally create smaller relocation sections than that packer. If I link Chromium for Android targeting ARM32 I get a .rel.dyn of size 174693 bytes, as compared to 371832 bytes with gold and the Android packer. Differential Revision: https://reviews.llvm.org/D39152 llvm-svn: 316775
* [X86][F16C] Fix btver2 AGU pipe schedulingSimon Pilgrim2017-10-271-3/+3
| | | | | | Use the store AGU for stores, and the load AGU needs to be the first pipe for loads llvm-svn: 316771
* [LoopPredication] Handle the case when the guard and the latch IV have ↵Artur Pilipenko2017-10-271-61/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | different offsets This is a follow up change for D37569. Currently the transformation is limited to the case when: * The loop has a single latch with the condition of the form: ++i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=. * The step of the IV used in the latch condition is 1. * The IV of the latch condition is the same as the post increment IV of the guard condition. * The guard condition is of the form i u< guardLimit. This patch enables the transform in the case when the latch is latchStart + i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=. And the guard is guardStart + i u< guardLimit Reviewed By: anna Differential Revision: https://reviews.llvm.org/D39097 llvm-svn: 316768
* [CodeGen] Fix -Wunused-private-field warning on lld-x86_64-darwin13.Clement Courbet2017-10-271-2/+0
| | | | llvm-svn: 316765
* [CodeGen][ExpandMemCmp][NFC] Simplify load sequence generation.Clement Courbet2017-10-271-40/+33
| | | | llvm-svn: 316763
* [LLVM-C] Publicly expose getters of MetadataType, TokenTypewhitequark2017-10-271-3/+6
| | | | | | | | | | | Patch by Robert Widmann. Expose getters for MetadataType and TokenType publicly in the C API. Discovered a need for these while trying to wrap the intrinsics API. Differential Revision: https://reviews.llvm.org/D38809 llvm-svn: 316762
* Fix BB after r316756 "[llvm-dwarfdump] - Teach verifier to report broken ↵George Rimar2017-10-271-1/+1
| | | | | | | | | | | DWARF expressions." Bot: http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/6255 Changed format of this message by mistake. llvm-svn: 316757
* [llvm-dwarfdump] - Teach verifier to report broken DWARF expressions.George Rimar2017-10-272-29/+45
| | | | | | | | | | | | | Patch improves next things: * Fixes assert/crash in getOpDesc when giving it a invalid expression op code. * DWARFExpression::print() called DWARFExpression::Operation::getEndOffset() which returned and used uninitialized field EndOffset. Patch fixes that. * Teaches verifier to verify DW_AT_location and error out on broken expressions. Differential revision: https://reviews.llvm.org/D39294 llvm-svn: 316756
* DAG: Fold fma (fneg x), K, y -> fma x, -K, yMatt Arsenault2017-10-271-0/+8
| | | | llvm-svn: 316753
* [GVN][NFC] Refactor loop iteration with foreachMax Kazantsev2017-10-271-6/+6
| | | | llvm-svn: 316748
* Revert rL316568 because of sudden performance drop on ARMMax Kazantsev2017-10-271-2/+8
| | | | llvm-svn: 316739
* Add subclass data to the FoldingSetNode for MemIntrinsicSDNodes.Sean Fertile2017-10-271-0/+2
| | | | | | | | | | | Not having the subclass data on an MemIntrinsicSDNodes means it was possible to try to fold 2 nodes with the same operands but differing MMO flags. This would trip an assertion when trying to refine the alignment between the 2 MachineMemOperands. Differential Revision: https://reviews.llvm.org/D38898 llvm-svn: 316737
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-2712-178/+350
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316724
* [PDB] Handle an empty globals hash table with no bucketsReid Kleckner2017-10-271-2/+3
| | | | llvm-svn: 316722
* Revert "[CGP] Merge empty case blocks if no extra moves are added."Balaram Makam2017-10-271-36/+11
| | | | | | This reverts commit r316711. The domtree isn't getting updated correctly. llvm-svn: 316721
* [WebAssembly] MC: Don't allow zero sized data segmentsSam Clegg2017-10-271-0/+8
| | | | | | | | | | | This ensures that each segment has a unique address. Without this, consecutive zero sized symbols would end up with the same address and the linker cannot map symbols to unique data segments. Differential Revision: https://reviews.llvm.org/D39107 llvm-svn: 316717
* InstructionSelectorImpl.h: Modularize/remove ODR violations by using a ↵David Blaikie2017-10-263-6/+7
| | | | | | static member function to expose the debug name llvm-svn: 316715
* [CGP] Merge empty case blocks if no extra moves are added.Balaram Makam2017-10-261-11/+36
| | | | | | | | | | | | | | | | Summary: Currently we skip merging when extra moves may be added in the header of switch instead of the case block, if the case block is used as an incoming block of a PHI. If all the incoming values of the PHIs are non-constants and the destination block is dominated by the switch block then extra moves are likely not added by ISel, so there is no need to skip merging in this case. Reviewers: efriedma, junbuml, davidxl, hfinkel, qcolombet Reviewed By: efriedma Subscribers: dberlin, kuhar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37343 llvm-svn: 316711
* [SimplifyIndVars] Shorten code by using SCEV helper [NFC]Philip Reames2017-10-261-7/+4
| | | | llvm-svn: 316709
* [ARM] Honor -mfloat-abi for libcall calling conventionEli Friedman2017-10-261-9/+1
| | | | | | | | | | | | | | | As far as I can tell, this matches gcc: -mfloat-abi determines the calling convention for all functions except those explicitly defined as soft-float in the ARM RTABI. This change only affects cases where the user specifies -mfloat-abi to override the default calling convention derived from the target triple. Fixes https://bugs.llvm.org//show_bug.cgi?id=34530. Differential Revision: https://reviews.llvm.org/D38299 llvm-svn: 316708
* Support/reg*: Roll some non-modular headers into their singular usesDavid Blaikie2017-10-263-226/+135
| | | | | | | | These headers have static variables in them, which would easily create ODR violations if the header was included in another header, and the constants were used by an inline function, for example. llvm-svn: 316706
* Do not add discriminator encoding for debug intrinsics.Dehao Chen2017-10-262-3/+5
| | | | | | | | | | | | | | Summary: There are certain requirements for debug location of debug intrinsics, e.g. the scope of the DILocalVariable should be the same as the scope of its debug location. As a result, we should not add discriminator encoding for debug intrinsics. Reviewers: dblaikie, aprantl Reviewed By: aprantl Subscribers: JDevlieghere, aprantl, bjope, sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D39343 llvm-svn: 316703
* [X86] Improve handling of UDIVREM8_ZEXT_HREG/SDIVREM8_SEXT_HREG to support ↵Craig Topper2017-10-262-15/+20
| | | | | | | | | | | | | | 64-bit extensions. If the extend type is 64-bits, emit a 32-bit -> 64-bit extend after the UDIVREM8_ZEXT_HREG/UDIVREM8_SEXT_HREG operation. This gives a shorter encoding for the second extend in the sext case, and allows us to completely remove the second extend in the zext case. This also adds known bit and num sign bits support for UDIVREM8_ZEXT_HREG/SDIVREM8_SEXT_HREG. Differential Revision: https://reviews.llvm.org/D38275 llvm-svn: 316702
* [X86] Teach the assembly parser to warn on duplicate registers in gather ↵Craig Topper2017-10-261-0/+71
| | | | | | | | | | instructions. Fixes PR32238. Differential Revision: https://reviews.llvm.org/D39077 llvm-svn: 316700
* [LICM] Restructure implicit exit handling to be more clear [NFCI]Philip Reames2017-10-261-27/+34
| | | | | | When going to explain this to someone else, I got tripped up by the complicated meaning of IsKnownNonEscapingObject in load-store promotion. Extract a helper routine and clarify naming/scopes to make this a bit more obvious. llvm-svn: 316699
* Support/reg*.h: Make headers include their dependenciesDavid Blaikie2017-10-263-0/+7
| | | | llvm-svn: 316696
* [COFF] Support ordinals in def files with space between @ and the numberMartin Storsjo2017-10-261-3/+8
| | | | | | | | | | Both GNU ld and MS link.exe support declaring ordinals this way. A test will be added in lld. Differential Revision: https://reviews.llvm.org/D39327 llvm-svn: 316690
* [x86] use an insert op to put one variable element into a constant of vectorsSanjay Patel2017-10-261-3/+51
| | | | | | | | Instead of loading (a potential ton of) scalar constants, load those as a vector and then insert into it. Differential Revision: https://reviews.llvm.org/D38756 llvm-svn: 316685
* Clear LastMappingSymbols and LastEMS(Info) when resetting the ↵Yichao Yu2017-10-262-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | ARM(AArch64)ELFStreamer Summary: This causes a segfault on ARM when (I think) the pass manager is used multiple times. Reset set the (last) current section to NULL without saving the corresponding LastEMSInfo back into the map. The next use of the streamer then save the LastEMSInfo for the NULL section leaving the LastEMSInfo mapping for the last current section (the one that was there before the reset) NULL which cause the LastEMSInfo to be set to NULL when the section is being used again. The reuse of the section (pointer) might mean that the map was holding dangling pointers previously which is why I went for clearing the map and resetting the info, making it as similar to the state right after the constructor run as possible. The AArch64 one doesn't have segfault (since LastEMS isn't a pointer) but it seems to have the same issue. The segfault is likely caused by https://reviews.llvm.org/D30724 which turns LastEMSInfo into a pointer. As mentioned above, it seems that the actual issue was older though. No test is included since the test is believed to be too complicated for such an obvious fix and not worth doing. Reviewers: llvm-commits, shankare, t.p.northover, peter.smith, rengolin Reviewed By: rengolin Subscribers: mgorny, aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38588 llvm-svn: 316679
* [DynamicLibrary] Fix build on musl libcKeno Fischer2017-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: On musl libc, stdin/out/err are defined as `FILE* const` globals, and their address is not implicitly convertible to void *, or at least gcc 6 doesn't allow it, giving errors like: ``` error: cannot initialize return object of type 'void *' with an rvalue of type 'FILE *const *' (aka '_IO_FILE *const *') EXPLICIT_SYMBOL(stderr); ^~~~~~~~~~~~~~~~~~~~~~~ ``` Add an explicit cast to fix that problem. Reviewers: marsupial, krytarowski, dim Reviewed By: dim Differential Revision: https://reviews.llvm.org/D39297 llvm-svn: 316672
* [MachineModuleInfoImpls] Replace qsort with array_pod_sortMandeep Singh Grang2017-10-261-10/+4
| | | | | | | | | | | | | | | | Summary: This seems to be the only place in llvm we directly call qsort. We can replace this with a call to array_pod_sort. Also minor cleanup of the sorting function. Reviewers: bkramer, Eugene.Zelenko, rafael Reviewed By: bkramer Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D39214 llvm-svn: 316671
* Reapply r316582 [Local] Fix a bug in the domtree update logic for ↵Balaram Makam2017-10-261-3/+7
| | | | | | | | | | | | MergeBasicBlockIntoOnlyPred. Summary: This reverts r316612 to reapply r316582. The buildbot failure was unrelated to this commit. Reviewers: Subscribers: llvm-svn: 316669
* Represent runtime preemption in the IR.Sean Fertile2017-10-2610-39/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we do not represent runtime preemption in the IR, which has several drawbacks: 1) The semantics of GlobalValues differ depending on the object file format you are targeting (as well as the relocation-model and -fPIE value). 2) We have no way of disabling inlining of run time interposable functions, since in the IR we only know if a function is link-time interposable. Because of this llvm cannot support elf-interposition semantics. 3) In LTO builds of executables we will have extra knowledge that a symbol resolved to a local definition and can't be preemptable, but have no way to propagate that knowledge through the compiler. This patch adds preemptability specifiers to the IR with the following meaning: dso_local --> means the compiler may assume the symbol will resolve to a definition within the current linkage unit and the symbol may be accessed directly even if the definition is not within this compilation unit. dso_preemptable --> means that the compiler must assume the GlobalValue may be replaced with a definition from outside the current linkage unit at runtime. To ease transitioning dso_preemptable is treated as a 'default' in that low-level codegen will still do the same checks it did previously to see if a symbol should be accessed indirectly. Eventually when IR producers emit the specifiers on all Globalvalues we can change dso_preemptable to mean 'always access indirectly', and remove the current logic. Differential Revision: https://reviews.llvm.org/D20217 llvm-svn: 316668
* AMDGPU: Handle s_buffer_load_dword hazard on SIMarek Olsak2017-10-261-0/+27
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D39171 llvm-svn: 316666
* [LSV] Avoid adding vectors of pointers as candidatesBjorn Pettersson2017-10-261-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We no longer add vectors of pointers as candidates for load/store vectorization. It does not seem to work anyway, but without this patch we can end up in asserts when trying to create casts between an integer type and the pointer of vectors type. The test case I've added used to assert like this when trying to cast between i64 and <2 x i16*>: opt: ../lib/IR/Instructions.cpp:2565: Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed. #0 PrintStackTraceSignalHandler(void*) #1 SignalHandler(int) #2 __restore_rt #3 __GI_raise #4 __GI_abort #5 __GI___assert_fail #6 llvm::CastInst::Create(llvm::Instruction::CastOps, llvm::Value*, llvm::Type*, llvm::Twine const&, llvm::Instruction*) #7 llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>::CreateBitOrPointerCast(llvm::Value*, llvm::Type*, llvm::Twine const&) #8 Vectorizer::vectorizeStoreChain(llvm::ArrayRef<llvm::Instruction*>, llvm::SmallPtrSet<llvm::Instruction*, 16u>*) Reviewers: arsenm Reviewed By: arsenm Subscribers: nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D39296 llvm-svn: 316665
* [LSV] Skip all non-byte sizes, not only less than eight bitsBjorn Pettersson2017-10-261-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The code comments indicate that no effort has been spent on handling load/stores when the size isn't a multiple of the byte size correctly. However, the code only avoided types smaller than 8 bits. So for example a load of an i28 could still be considered as a candidate for vectorization. This patch adjusts the code to behave according to the code comment. The test case used to hit the following assert when trying to use "cast" an i32 to i28 using CreateBitOrPointerCast: opt: ../lib/IR/Instructions.cpp:2565: Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed. #0 PrintStackTraceSignalHandler(void*) #1 SignalHandler(int) #2 __restore_rt #3 __GI_raise #4 __GI_abort #5 __GI___assert_fail #6 llvm::CastInst::Create(llvm::Instruction::CastOps, llvm::Value*, llvm::Type*, llvm::Twine const&, llvm::Instruction*) #7 llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>::CreateBitOrPointerCast(llvm::Value*, llvm::Type*, llvm::Twine const&) #8 (anonymous namespace)::Vectorizer::vectorizeLoadChain(llvm::ArrayRef<llvm::Instruction*>, llvm::SmallPtrSet<llvm::Instruction*, 16u>*) Reviewers: arsenm Reviewed By: arsenm Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39295 llvm-svn: 316663
* [mips] Fix (dis)assembly of abs.fmt for micromipsSimon Dardis2017-10-262-7/+16
| | | | | | | | | | | These instructions were previously marked as codegen only preventing them from being assembled as microMIPS or disassembled. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D39123 llvm-svn: 316656
* [mips] Fix PR35071Simon Dardis2017-10-261-13/+12
| | | | | | | | | | | | | | | | | | | | PR35071 exposed the fact that MipsInstrInfo::removeBranch did not walk past debug instructions when removing branches for the control flow optimizer, which lead to duplicated conditional branches. If the target of the branch was a removable block, only the conditional branch in the terminating position would have it's MBB operands updated, leaving the first branch with a dangling MBB operand. The MIPS long branch pass would then trigger an assertion when attempting to examine the instruction with dangling MBB operand. This resolves PR35071. Thanks to Alex Richardson for reporting the issue! Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39288 llvm-svn: 316654
* [PowerPC] Use record-form instruction for Less-or-Equal -1 and ↵Hiroshi Inoue2017-10-261-30/+39
| | | | | | | | | | | Greater-or-Equal 1 Currently a record-form instruction is used for comparison of "greater than -1" and "less than 1" by modifying the predicate (e.g. LT 1 into LE 0) in addition to the naive case of comparison against 0. This patch also enables emitting a record-form instruction for "less than or equal to -1" (i.e. "less than 0") and "greater than or equal to 1" (i.e. "greater than 0") to increase the optimization opportunities. Differential Revision: https://reviews.llvm.org/D38941 llvm-svn: 316647
* Tidy up CountingFunctionInserter a little. NFC.Hans Wennborg2017-10-261-8/+4
| | | | | | | Use StringRef for CountingFunctionName, remove erroneous comment copied from InstructionNamer, and drop some trailing whitespace. llvm-svn: 316644
* [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell ↵Craig Topper2017-10-263-3/+6
| | | | | | | | check function so it can use the correct table based on variant. I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants. llvm-svn: 316641
OpenPOWER on IntegriCloud