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* When converting a CopyFromReg to a copy instruction, use the register class ↵Evan Cheng2008-09-161-5/+24
| | | | | | of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. llvm-svn: 56258
* Change SelectionDAG::getConstantPool to always set the alignment of theDan Gohman2008-09-162-7/+20
| | | | | | | | | | | | | | | | | | | | ConstantPoolSDNode, using the target's preferred alignment for the constant type. In LegalizeDAG, when performing loads from the constant pool, the ConstantPoolSDNode's alignment is used in the calls to getLoad and getExtLoad. This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly choosing the ABI alignment for constant pool loads when Alignment == 0. The incorrect alignment is only a performance issue when ABI alignment does not equal preferred alignment (i.e., on x86 it was generating MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI alignment for 128bit vectors is forced to 1 byte.) Patch by Paul Redmond! llvm-svn: 56253
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-1621-143/+130
| | | | | | Apologies for the thrashing. llvm-svn: 56251
* Include the alignment value when displaying ConstantPoolSDNodes.Dan Gohman2008-09-161-0/+1
| | | | llvm-svn: 56250
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-1621-130/+143
| | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. llvm-svn: 56249
* Fix these comments to reflect current reality. Surprisingly,Dan Gohman2008-09-161-1/+2
| | | | | | | MachineConstantPool::getConstantPoolIndex actually expects a log2-encoded alignment. llvm-svn: 56248
* Finally re-apply r46959. This is made feasible by the combinationDan Gohman2008-09-161-2/+2
| | | | | | of r56230, r56232, and r56246. llvm-svn: 56247
* Improve instcombine's handling of integer min and max in two ways:Dan Gohman2008-09-162-34/+115
| | | | | | | | | | | | | | | | - Recognize expressions like "x > -1 ? x : 0" as min/max and turn them into expressions like "x < 0 ? 0 : x", which is easily recognizable as a min/max operation. - Refrain from folding expression like "y/2 < 1" to "y < 2" when the comparison is being used as part of a min or max idiom, like "y/2 < 1 ? 1 : y/2". In that case, the division has another use, so folding doesn't eliminate it, and obfuscates the min/max, making it harder to recognize as a min/max operation. These benefit ScalarEvolution, CodeGen, and anything else that wants to recognize integer min and max. llvm-svn: 56246
* AllocateRWXMemory -> AllocateRWX.Evan Cheng2008-09-161-1/+1
| | | | llvm-svn: 56244
* Don't take the time to CheckDAGForTailCallsAndFixThem when tail callsDan Gohman2008-09-162-4/+10
| | | | | | | are not enabled. Instead just omit the tail call flag when calls are created. llvm-svn: 56235
* Re-enables the new vector select in the bitcode reader, by modifying theDan Gohman2008-09-162-12/+29
| | | | | | | | | | | | | | | | | | | | | | bitcode reader/writer as follows: - add and use new bitcode FUNC_CODE_INST_VSELECT to handle the llvm select opcode using either i1 or [N x i1] as the selector. - retain old BITCODE FUNC_CODE_INST_SELECT in the bitcode reader to handle select on i1 for backwards compatibility with existing bitcode files. - re-enable the vector-select.ll test program. Also, rename the recently added bitcode opcode FUNC_CODE_INST_VCMP to FUNC_CODE_INST_CMP2 and make the bitcode writer use it to handle fcmp/icmp on scalars or vectors. In the bitcode writer, use FUNC_CODE_INST_CMP for vfcmp/vicmp only. In the bitcode reader, have FUNC_CODE_INST_CMP handle icmp/fcmp returning bool, for backwards compatibility with existing bitcode files. Patch by Preston Gurd! llvm-svn: 56233
* Teach ScalarEvolution to consider loop preheaders in the search forDan Gohman2008-09-151-8/+38
| | | | | | | an if statement that guards a loop, to allow indvars to avoid smax operations in more situations. llvm-svn: 56232
* Live intervals for live-in registers should begin at the beginning of a ↵Owen Anderson2008-09-151-7/+11
| | | | | | | | | basic block, not at the first instruction. Also, their valno's should have an unknown def. This has no effect currently, but was causing issues when StrongPHIElimination was enabled. llvm-svn: 56231
* Teach LSR to optimize away SMAX operations for tripcounts in commonDan Gohman2008-09-151-0/+127
| | | | | | | | | cases. See the comment above OptimizeSMax for the full story, and the testcase for an example. This cancels out a pessimization commonly attributed to indvars, and will allow us to lift some of the artificial throttles in indvars, rather than add new ones. llvm-svn: 56230
* Fixed Bug 2751Bruno Cardoso Lopes2008-09-152-4/+4
| | | | | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=2751 Abicall was enabled even when static code model was provided in the command line. The correct behavior is to disable abicall when static is specified. llvm-svn: 56228
* Re-enable SelectionDAG CSE for calls. It matters in the case ofDan Gohman2008-09-151-6/+20
| | | | | | libcalls, as in this testcase on ARM. llvm-svn: 56226
* Correctly update kill infos after extending a live range and merge 2 val#'s; ↵Evan Cheng2008-09-151-3/+8
| | | | | | fix 56165 - do not mark val# copy field if the copy does not define the val#. llvm-svn: 56199
* Fix WriteAsOperand to not emit a leading space character. AdjustDan Gohman2008-09-142-34/+60
| | | | | | | | | | | | | | | | | | its callers to emit a space character before calling it when a space is needed. This fixes several spurious whitespace issues in ScalarEvolution's debug dumps. See the test changes for examples. This also fixes odd space-after-tab indentation in the output for switch statements, and changes calls from being printed like this: call void @foo( i32 %x ) to this: call void @foo(i32 %x) llvm-svn: 56196
* adjust last patch per review feedbackDale Johannesen2008-09-141-3/+3
| | | | llvm-svn: 56194
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-1316-66/+69
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* Fix PR2792: treat volatile loads as writing memory somewhere.Duncan Sands2008-09-131-3/+11
| | | | | | Treat stores as reading memory, just to play safe. llvm-svn: 56188
* Fix random abort.Evan Cheng2008-09-131-2/+4
| | | | llvm-svn: 56184
* Define CallSDNode, an SDNode subclass for use with ISD::CALL.Dan Gohman2008-09-1314-188/+194
| | | | | | | | | | | | | Currently it just holds the calling convention and flags for isVarArgs and isTailCall. And it has several utility methods, which eliminate magic 5+2*i and similar index computations in several places. CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle nodes that are not CSE'd gracefully. llvm-svn: 56183
* Typo.Evan Cheng2008-09-131-3/+3
| | | | llvm-svn: 56182
* Rely on instruction format to determine so_reg operand for now.Evan Cheng2008-09-131-1/+5
| | | | llvm-svn: 56181
* Revert 56176. All those instruction formats are still needed.Evan Cheng2008-09-134-49/+84
| | | | llvm-svn: 56180
* Accidentially flipped the condition.Evan Cheng2008-09-131-1/+1
| | | | llvm-svn: 56179
* Add debug dumps.Evan Cheng2008-09-131-0/+5
| | | | llvm-svn: 56178
* Eliminate unnecessary instruction formats.Evan Cheng2008-09-124-90/+51
| | | | llvm-svn: 56176
* Addrmode 1 S bit can be dynamically set. Look for CPSR def.Evan Cheng2008-09-122-28/+42
| | | | llvm-svn: 56172
* Rewrite address mode 1 code emission routines.Evan Cheng2008-09-122-129/+104
| | | | llvm-svn: 56171
* On some targets, non-move instructions can become move instructions because ↵Evan Cheng2008-09-121-14/+28
| | | | | | | | | | | | of coalescing. e.g. vr2 = OR vr0, vr1 => vr2 = OR vr1, vr1 // after coalescing vr0 with vr1 Update the value# of the destination register with the copy instruction if that happens. llvm-svn: 56165
* Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* andDan Gohman2008-09-125-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | ConstantFP* instead of APInt and APFloat directly. This reduces the amount of time to create ConstantSDNode and ConstantFPSDNode nodes when ConstantInt* and ConstantFP* respectively are already available, as is the case in SelectionDAGBuild.cpp. Also, it reduces the amount of time to legalize constants into constant pools, and the amount of time to add ConstantFP operands to MachineInstrs, due to eliminating ConstantInt::get and ConstantFP::get calls. It increases the amount of work needed to create new constants in cases where the client doesn't already have a ConstantInt* or ConstantFP*, such as legalize expanding 64-bit integer constants to 32-bit constants. And it adds a layer of indirection for the accessor methods. But these appear to be outweight by the benefits in most cases. It will also make it easier to make ConstantSDNode and ConstantFPNode more consistent with ConstantInt and ConstantFP. llvm-svn: 56162
* Pass "earlyclobber" bit through to machineDale Johannesen2008-09-123-5/+20
| | | | | | | representation; coalescer and RA need to know about it. No functional change. llvm-svn: 56161
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-1242-476/+535
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* Rather than marking all internal globals "Ref"Duncan Sands2008-09-121-17/+11
| | | | | | | | | | | | | | | | when a readonly declaration is called, set a flag. This is faster and uses less memory. In theory it is less accurate, because before only those internal globals that were read by someone were being marked "Ref", but now all are. But in practice, thanks to other passes, all internal globals of the kind considered here will be both read and stored to: those only read will have been turned into constants, and those only stored to will have been deleted. llvm-svn: 56143
* The sequence for ppcf128 compares was not IEEEDale Johannesen2008-09-121-4/+6
| | | | | | safe in the presence of NaNs. llvm-svn: 56136
* On 64-bit targets, change 32-bit getelementptr indices to be 64-bitDan Gohman2008-09-111-1/+12
| | | | | | | getelementptr indices, inserting an explicit cast if necessary. This helps expose the sign-extension operation to other optimizations. llvm-svn: 56133
* Fix a vectorshuffle instcombine bug introduced by r55995.Dan Gohman2008-09-111-1/+4
| | | | | | Patch by Nicolas Capens! llvm-svn: 56129
* udpate header comment: s/VP/VFP/Jim Grosbach2008-09-111-1/+1
| | | | llvm-svn: 56126
* When tailcallopt is enabled all fastcc calls must have an aligned argument ↵Arnold Schwaighofer2008-09-111-1/+1
| | | | | | stack size. Add a test case. llvm-svn: 56119
* Fix PR2748. Avoid coalescing physical register with virtual register which ↵Evan Cheng2008-09-112-0/+70
| | | | | | | | | | | would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. llvm-svn: 56118
* Fix a bug in ANY_EXTEND handling that was breaking 403.gcc on X86-64 in fast ↵Owen Anderson2008-09-111-2/+7
| | | | | | isel. llvm-svn: 56117
* Fix comment typo.Duncan Sands2008-09-111-1/+1
| | | | llvm-svn: 56116
* Intrinsics don't touch internal global variablesDuncan Sands2008-09-111-2/+4
| | | | | | | (unless passed one via a parameter), even if they are IntrWriteMem. llvm-svn: 56115
* Fix a copy+paste bug that Duncan spotted. For severalDan Gohman2008-09-111-1/+1
| | | | | | | cases it was still getting lucky and detecting overflow but it was clearly incorrect. llvm-svn: 56113
* Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister ↵Evan Cheng2008-09-111-1/+2
| | | | | | check. llvm-svn: 56112
* Intrinsics don't read these kinds of globalDuncan Sands2008-09-111-5/+7
| | | | | | variables. llvm-svn: 56105
* Fix a 80 column violation.Evan Cheng2008-09-111-1/+2
| | | | llvm-svn: 56097
* The version of AtomicSDNode::AtomicSDNode used (only) forDale Johannesen2008-09-111-6/+6
| | | | | | | | | | | | | cmp-and-swap reversed the Cmp and Swap arguments; comments make it clear this is unintentional. Unfortunately, the x86 BE had a compensating reversal, which is removed here. PPC is OK. From inspection of the Alpha code I think it is OK, but if somebody has that platform please check it out. I cannot test on that platform. llvm-svn: 56091
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