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* [WebAssembly] Add 'final' to some classes. NFC.Dan Gohman2015-11-252-2/+2
| | | | llvm-svn: 254073
* [WebAssembly] Whitespace consistency. NFC.Dan Gohman2015-11-252-2/+0
| | | | llvm-svn: 254071
* fix typo; NFCSanjay Patel2015-11-251-1/+1
| | | | llvm-svn: 254069
* [PowerPC] Don't generate mfocrf on the e500mcHal Finkel2015-11-251-1/+1
| | | | | | | | | The e500mc does not actually support the mfocrf instruction; update the processor definitions to reflect that fact. Patch by Tom Rix (with some test-case cleanup by me). llvm-svn: 254064
* Fix some places where we were assuming that memory type had been legalizedEric Christopher2015-11-252-3/+2
| | | | | | | | | | to a simple type when lowering a truncating store of a vector type. In this case for an EVT we'll return Expand as we should in all of the cases anyhow. The testcase triggered at the one in VectorLegalizer::LegalizeOp, inspection found the rest. llvm-svn: 254061
* AVX-512: Fixed a bug in VPERMT2* intrinsic.Elena Demikhovsky2015-11-253-51/+138
| | | | | | | | | It was wrong order of operands (from intrinsic to DAG node). I added more strict type specification for instruction selection. Differential Revision: http://reviews.llvm.org/D14942 llvm-svn: 254059
* [PGO] Convert InstrProfRecord based serialization methods to use common C ↵Xinliang David Li2015-11-251-35/+97
| | | | | | | | | | | | | | | | methods 1. Convert serialization methods using InstrProfRecord as source into C (impl) interfaces using Closure. 2. Reimplement InstrProfRecord serialization method to use new C interface as dummy wrapper. Now it is ready to implement wrapper for runtime value profile data. (The new code need better source location -- but not changed in this patch to minimize diffs. ) llvm-svn: 254057
* [PGO] convert a subset of C++ interfaces into C (for sharing) (NFC)Xinliang David Li2015-11-251-28/+10
| | | | llvm-svn: 254056
* Move member functions closer to others of the same class (NFC)Xinliang David Li2015-11-251-14/+16
| | | | llvm-svn: 254055
* AsmParser: Make the code for parsing unnamed aliases more closely resemble ↵Peter Collingbourne2015-11-251-18/+27
| | | | | | | | | | that for unnamed globals. This fixes parsing of forward references to unnamed aliases. While here, remove an unnecessary isa check. llvm-svn: 254054
* [OperandBundles] Extract duplicated code into a helper function, NFCSanjoy Das2015-11-252-10/+2
| | | | llvm-svn: 254047
* [InstCombine] Don't drop operand bundlesSanjoy Das2015-11-251-3/+10
| | | | | | | | | | Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14857 llvm-svn: 254046
* Fix function naming (NFC)Xinliang David Li2015-11-251-2/+2
| | | | llvm-svn: 254045
* Revert r253528: "[X86] Enable shrink-wrapping by default."Hans Wennborg2015-11-251-5/+0
| | | | | | | | | This caused PR25607 and also caused Chromium to crash on start-up. (Also had to update test/CodeGen/X86/avx-splat.ll, which was committed after shrink wrapping was enabled.) llvm-svn: 254044
* Fix an asan error where NumElements > 32 for at least one case inKaelyn Takata2015-11-251-2/+3
| | | | | | test/CodeGen/X86/avg.ll. llvm-svn: 254043
* [PGO] Revert revision r254021,r254028,r254035Rong Xu2015-11-247-939/+2
| | | | | | Revert the above revision due to multiple issues. llvm-svn: 254040
* [PGO] Add mapper callback to interfaces retrieving value data for site (NFC)Xinliang David Li2015-11-241-11/+13
| | | | | | | This allows cleaner implementation and merging retrieving/mapping in one pass. llvm-svn: 254038
* [ThinLTO] Add option to limit importing based on instruction countTeresa Johnson2015-11-241-0/+12
| | | | | | | | Add a simple initial heuristic to control importing based on the number of instructions recorded in the function's summary. Add option to control the limit, and test using option. llvm-svn: 254036
* SamplePGO - Add test for hot/cold inlined functions.Diego Novillo2015-11-241-17/+47
| | | | | | | | | | | | | | | | | | | | | | | When the original binary is executed and sampled, the resulting profile contains information on the original inline stack. We currently follow the original inline plan if we notice that the inlined callsite has more than 0 samples to it. A better way is to determine whether the callsite is actually worth inlining. If the callsite accumulates a small fraction of the samples spent in the parent function, then we don't want to bother inlining it (as it means that the callsite is actually cold). This patch introduces a threshold expressed in percentage of samples in relation to the parent function. If the callsite uses less than N% of the total samples used by its parent, the original inline decision is not re-applied. I've set the threshold to the very arbitrary value of 5%. I'm yet to do any actual experiments to see what's a good value. I wanted to separate the basic mechanism from the tuning. llvm-svn: 254034
* [PGO] Fix build errors in x86_64-darwinRong Xu2015-11-242-3/+3
| | | | | | Fix buildbot failure for x86_64-darwin due to r254021 llvm-svn: 254028
* [PGO] MST based PGO instrumentation infrastructureRong Xu2015-11-247-2/+939
| | | | | | | | | | | | This patch implements a minimum spanning tree (MST) based instrumentation for PGO. The use of MST guarantees minimum number of CFG edges getting instrumented. An addition optimization is to instrument the less executed edges to further reduce the instrumentation overhead. The patch contains both the instrumentation and the use of the profile to set the branch weights. Differential Revision: http://reviews.llvm.org/D12781 llvm-svn: 254021
* [ThinLTO] Refactor function body scan during importing into helper (NFC)Teresa Johnson2015-11-241-36/+27
| | | | llvm-svn: 254020
* [RuntimeDyld] Fix a class of arithmetic errors introduced in r253918Sanjoy Das2015-11-241-4/+4
| | | | | | | | | | | r253918 had refactored expressions like "A - B.Address + C" to "A - B.getAddressWithOffset(C)". This is incorrect, since the latter really computes "A - B.Address - C". None of the tests I can run locally on x86 broke due to this bug, but it is the current suspect for breakage on the AArch64 buildbots. llvm-svn: 254017
* [X86][FMA] Optimize FNEG(FMA) PatternsSimon Pilgrim2015-11-241-0/+29
| | | | | | | | | | X86 needs to use its own FMA opcodes, preventing the standard FNEG(FMA) pattern table recognition method used by other platforms. This patch adds support for lowering FNEG(FMA(X,Y,Z)) into a single suitably negated FMA instruction. Fix for PR24364 Differential Revision: http://reviews.llvm.org/D14906 llvm-svn: 254016
* LiveVariables should not clobber MachineOperand::IsDead, ::IsKill on ↵Matthias Braun2015-11-241-2/+6
| | | | | | | | | | reserved physical registers Patch by Nick Johnson <Nicholas.Paul.Johnson@deshawresearch.com> Differential Revision: http://reviews.llvm.org/D14875 llvm-svn: 254012
* [ThinLTO] Enable iterative importing in FunctionImport passTeresa Johnson2015-11-241-2/+36
| | | | | | | | | | | Analyze imported function bodies and add any new external calls to the worklist for importing. Currently no controls on the importing so this will end up importing everything possible in the call tree below the importing module. Basic profitability checks coming next. Update test to check for iteratively inlined functions. llvm-svn: 254011
* [X86] Fix several issues related to X86's psadbw instruction.Cong Hou2015-11-245-33/+35
| | | | | | | | | | | | | | | | This patch fixes the following issues: 1. Fix the return type of X86psadbw: it should not be the same type of inputs. For vNi8 inputs the output should be vMi64, where M = N/8. 2. Fix the return type of int_x86_avx512_psad_bw_512 accordingly. 3. Fix the definiton of PSADBW, VPSADBW, and VPSADBWY accordingly. 4. Adjust the return type when building a DAG node of X86ISD::PSADBW type. 5. Update related tests. Differential revision: http://reviews.llvm.org/D14897 llvm-svn: 254010
* [ThinLTO] Handle previously imported and promoted locals in module linkerTeresa Johnson2015-11-241-2/+2
| | | | | | | | | | | The new function import pass exposed an issue when we import references to local values on multiple importing passes. They are renamed on each import pass, and we need to ensure that the already promoted and renamed references existing in the dest module are correctly identified and updated so that they aren't spuriously renamed again (due to a perceived conflict with the newly linked reference). llvm-svn: 254009
* [Utils] Put includes in correct order. NFC.Weiming Zhao2015-11-248-10/+8
| | | | | | | | | | | | | | | | | | | Summary: Followed the guidelines in: http://llvm.org/docs/CodingStandards.html#include-style However, I noticed that uppercase named headers come before lowercase ones throughout the codebase. So kept them as is. Patch by Mandeep Singh Grang <mgrang@codeaurora.org> Reviewers: majnemer, davide, jmolloy, atrick Subscribers: sanjoy Differential Revision: http://reviews.llvm.org/D14939 llvm-svn: 254005
* [PGO] Small interface change to be profile rt ready Xinliang David Li2015-11-241-17/+3
| | | | | | | | Convert two C++ static member functions to be C APIs. This is one of the many steps to get ready to share VP writer code with profiler runtime. llvm-svn: 253999
* [InstCombine] fix propagation of fast-math-flagsSanjay Patel2015-11-241-10/+5
| | | | | | | Noticed while working on D4583: http://reviews.llvm.org/D4583 llvm-svn: 253997
* use convenience function for copying IR flags; NFCISanjay Patel2015-11-241-12/+2
| | | | llvm-svn: 253996
* Minor refactor to make VP writing more efficientXinliang David Li2015-11-241-3/+1
| | | | llvm-svn: 253994
* Add vector types for intrinsicsKrzysztof Parzyszek2015-11-241-1/+11
| | | | | Author: Ron Lieberman <ronl@codeaurora.org> llvm-svn: 253992
* [ThinLTO] Fix FunctionImport alias checking and testTeresa Johnson2015-11-241-4/+5
| | | | | | | Skip imports for weak_any aliases as well. Fix the test to check non-import of weak aliases and functions, and import of normal alias. llvm-svn: 253991
* [x86] remove duplicate movq instruction defs (PR25554)Sanjay Patel2015-11-242-27/+13
| | | | | | | | | | | | | | | | | | | | | | | | | We had duplicated definitions for the same hardware '[v]movq' instructions. For example with SSE: def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))))], IIC_SSE_MOVDQ>; def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), "mov{d|q}\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector GR64:$src)))], IIC_SSE_MOVDQ>, Sched<[WriteMove]>; As shown in the test case and PR25554: https://llvm.org/bugs/show_bug.cgi?id=25554 This causes us to miss reusing an operand because later passes don't know these 'movq' are the same instruction. This patch deletes one pair of these defs. Sadly, this won't fix the original test case in the bug report. Something else is still broken. Differential Revision: http://reviews.llvm.org/D14941 llvm-svn: 253988
* [Hexagon] Add missing include of <cctype>Krzysztof Parzyszek2015-11-241-0/+1
| | | | | | | Lack thereof breaks Windows builds due to the use of std::isspace in HexagonInstrInfo.cpp. llvm-svn: 253987
* [Hexagon] Bring HexagonInstrInfo up to dateKrzysztof Parzyszek2015-11-249-1173/+3004
| | | | llvm-svn: 253986
* Add new vector types for 512-, 1024- and 2048-bit vectorsKrzysztof Parzyszek2015-11-241-0/+22
| | | | | | | | Those types are needed to implement instructions for Hexagon Vector Extensions (HVX): 16x32, 16x64, 32x16, 32x32, 32x64, 64x8, 64x16, 64x32, 128x8, 128x16, 256x8, 512x1, and 1024x1. llvm-svn: 253978
* AMDGPU: Split LDS vector loadsMatt Arsenault2015-11-242-2/+3
| | | | | | If properly aligned this could allow using ds_read_b64. llvm-svn: 253975
* AMDGPU: Split x8 and x16 vector loads instead of scalarizeMatt Arsenault2015-11-242-1/+15
| | | | | | | | The one regression in the builtin tests is in the read2 test which now (again) has many extra copies, but this should be solved once the pass is replaced with a DAG combine. llvm-svn: 253974
* Fix build after r253954Ismail Donmez2015-11-241-1/+1
| | | | llvm-svn: 253969
* Let SelectionDAG start to use probability-based interface to add successors.Cong Hou2015-11-249-233/+265
| | | | | | | | | | | | | | | | | | | | | | | | The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes. 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights. 3. Use new interfaces in all other passes. 4. Remove old interfaces. This the second patch above. In this patch SelectionDAG starts to use probability-based interfaces in MBB to add successors but other MC passes are still using weight-based interfaces. Therefore, we need to maintain correct weight list in MBB even when probability-based interfaces are used. This is done by updating weight list in probability-based interfaces by treating the numerator of probabilities as weights. This change affects many test cases that check successor weight values. I will update those test cases once this patch looks good to you. Differential revision: http://reviews.llvm.org/D14361 llvm-svn: 253965
* Add a FunctionImporter helper to perform summary-based cross-module function ↵Mehdi Amini2015-11-244-1/+242
| | | | | | | | | | | | | | | | | importing Summary: This is a helper to perform cross-module import for ThinLTO. Right now it is importing naively every possible called functions. Reviewers: tejohnson Subscribers: dexonsmith, llvm-commits Differential Revision: http://reviews.llvm.org/D14914 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 253954
* [X86][SSE] Detect AVG pattern during instruction combine for SSE2/AVX2/AVX512BW.Cong Hou2015-11-243-4/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch detects the AVG pattern in vectorized code, which is simply c = (a + b + 1) / 2, where a, b, and c have the same type which are vectors of either unsigned i8 or unsigned i16. In the IR, i8/i16 will be promoted to i32 before any arithmetic operations. The following IR shows such an example: %1 = zext <N x i8> %a to <N x i32> %2 = zext <N x i8> %b to <N x i32> %3 = add nuw nsw <N x i32> %1, <i32 1 x N> %4 = add nuw nsw <N x i32> %3, %2 %5 = lshr <N x i32> %N, <i32 1 x N> %6 = trunc <N x i32> %5 to <N x i8> and with this patch it will be converted to a X86ISD::AVG instruction. The pattern recognition is done when combining instructions just before type legalization during instruction selection. We do it here because after type legalization, it is much more difficult to do pattern recognition based on many instructions that are doing type conversions. Therefore, for target-specific instructions (like X86ISD::AVG), we need to take care of type legalization by ourselves. However, as X86ISD::AVG behaves similarly to ISD::ADD, I am wondering if there is a way to legalize operands and result types of X86ISD::AVG together with ISD::ADD. It seems that the current design doesn't support this idea. Tests are added for SSE2, AVX2, and AVX512BW and both i8 and i16 types of variant vector sizes. Differential revision: http://reviews.llvm.org/D14761 llvm-svn: 253952
* [DIE] Make DIE.h NDEBUG conditional-free.Davide Italiano2015-11-241-26/+18
| | | | | | Switch dump()/print() method definitions to LLVM_DUMP_METHOD instead. llvm-svn: 253945
* [RuntimeDyld] Avoid unused-private-field warning; NFCSanjoy Das2015-11-231-1/+5
| | | | | | Fixes the no asserts -Werror,-Wunused-private-field build. llvm-svn: 253933
* [WebAssembly] Don't print the types of memory_size and grow_memoryDan Gohman2015-11-231-4/+4
| | | | | | This matches the current spec, for now. llvm-svn: 253931
* [PGO] In llvm-profdata text dump, add comment lines as annotationsXinliang David Li2015-11-231-1/+4
| | | | llvm-svn: 253930
* Revert r253923.Krzysztof Parzyszek2015-11-231-22/+0
| | | | | | Per Eric's request. llvm-svn: 253928
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