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* [X86] Add encoding information for the AVX5124FMAPS and AVX5124VNNIW ↵Craig Topper2018-06-023-1/+78
| | | | | | | | | | instructions so they can be assembled and disassembled. These instructions are unusual in that they operate on 4 consecutive registers so supporting them in codegen will be more difficult than normal. Includes an assembler check to warn if the source register is not the first register of a 4 register group. llvm-svn: 333812
* [PM/LoopUnswitch] Fix how the cloned loops are handled when updating analyses.Chandler Carruth2018-06-021-44/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I noticed this issue because we didn't put the primary cloned loop into the `NonChildClonedLoops` vector and so never iterated on it. Once I fixed that, it made it clear why I had to do a really complicated and unnecesasry dance when updating the loops to remain in canonical form -- I was unwittingly working around the fact that the primary cloned loop wasn't in the expected list of cloned loops. Doh! Now that we include it in this vector, we don't need to return it and we can consolidate the update logic as we correctly have a single place where it can be handled. I've just added a test for the iteration order aspect as every time I changed the update logic partially or incorrectly here, an existing test failed and caught it so that seems well covered (which is also evidenced by the extensive working around of this missing update). Reviewers: asbirlea, sanjoy Subscribers: mcrosier, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D47647 llvm-svn: 333811
* [DebugInfo] Refactoring DIType::setFlags to DIType::cloneWithFlags, NFCRoman Tereshin2018-06-011-5/+9
| | | | | | | | | | | | | | | | | | and using the latter in DIBuilder::createArtificialType and DIBuilder::createObjectPointerType methods as well as introducing mirroring DISubprogram::cloneWithFlags and DIBuilder::createArtificialSubprogram methods. The primary goal here is to add createArtificialSubprogram to support a pass downstream while keeping the method consistent with the existing ones and making sure we don't encourage changing already created DI-nodes. Reviewed By: aprantl Differential Revision: https://reviews.llvm.org/D47615 llvm-svn: 333806
* [X86] Do something sensible when an expand load intrinsic is passed a 0 mask.Craig Topper2018-06-011-1/+1
| | | | | | Previously we just returned undef, but really we should be returning the pass thru input. We also need to make sure we preserve the chain output that the original intrinsic node had to maintain connectivity in the DAG. So we should just return the incoming chain as the output chain. llvm-svn: 333804
* Add a debug dump for DbgValueHistoryMapVedant Kumar2018-06-013-0/+37
| | | | | | | | | This makes it easier to inspect the results of DbgValueHistoryCalculator. Differential Revision: https://reviews.llvm.org/D47663 llvm-svn: 333801
* [X86] Add isel patterns to use vexpand with zero masking when the passthru ↵Craig Topper2018-06-011-0/+4
| | | | | | value is a zero vector. llvm-svn: 333800
* Move some function declarations out of WindowsSupport.hZachary Turner2018-06-016-14/+5
| | | | | | | | | | | | | | | | | | The idea behind WindowsSupport.h is that it's in the source directory so that windows.h'isms don't leak out into the larger LLVM project. To that end, any symbol that references a symbol from windows.h must be in this private header, and not in a public header. However, we had some useful utility functions in WindowsSupport.h which have no dependency on the Windows API, but still only make sense on Windows. Those functions should be usable outside of Support since there is no risk of causing a windows.h leak. Although this introduces some preprocessor logic in some header files, It's not too egregious and it's better than the alternative of duplicating a ton of code. Differential Revision: https://reviews.llvm.org/D47662 llvm-svn: 333798
* [ConstantFold] Disallow folding vector geps into bitcastsKarl-Johan Karlsson2018-06-011-1/+5
| | | | | | | | | | | | | | | | | | | Summary: Getelementptr returns a vector of pointers, instead of a single address, when one or more of its arguments is a vector. In such case it is not possible to simplify the expression by inserting a bitcast of operand(0) into the destination type, as it will create a bitcast between different sizes. Reviewers: majnemer, mkuper, mssimpso, spatel Reviewed By: spatel Subscribers: lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D46379 llvm-svn: 333783
* [InstCombine] fix vector shuffle transform to replace undef elements (PR37648)Sanjay Patel2018-06-011-0/+16
| | | | | | | | | | | | | | This bug: https://bugs.llvm.org/show_bug.cgi?id=37648 ...was created with the enhancement to this transform with rL332479. The urem test shows the disaster potential: any undef divisor lane makes the whole op undef. The test diffs show that vector demanded elements turns some of the potential, but not all, unused binop operands back into undef already. llvm-svn: 333782
* [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructionsSimon Atanasyan2018-06-011-53/+30
| | | | | | | | | | | | | | | The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
* [mips] Extend list of relocations supported by the `.reloc` directiveSimon Atanasyan2018-06-013-1/+80
| | | | | | | Supporting GOT and TLS related relocations by the `.reloc` directive is useful for purpose of testing various tools like a linker, for example. llvm-svn: 333773
* [Hexagon] Avoid UB when shifting unsigned integer left by 32Krzysztof Parzyszek2018-06-011-3/+4
| | | | llvm-svn: 333771
* [ThinLTOBitcodeWriter] Emit summaries for regular LTO modulesVlad Tsyrklevich2018-06-011-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Emit summaries for bitcode modules that are only destined for the regular LTO portion of the build so they can participate in summary-based dead stripping. This change reduces the size of a nacl_helper build with cfi-icall enabled by 7%, removing the majority of the overhead due to enabling cfi-icall. The cfi-icall size increase was caused by compiling in lots of unused code and cfi-icall generating jumptable references to unused symbols that could no longer be removed by -Wl,-gc-sections. Increasing the visibility of summary-based dead stripping prevented jumptable entries being created for unused symbols from the regular LTO portion of the build. Reviewers: pcc Reviewed By: pcc Subscribers: dschuff, mehdi_amini, inglorion, eraman, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D47594 llvm-svn: 333768
* [DAG] Avoid checking for consecutive stores in store merge. NFCI.Nirav Dave2018-06-011-319/+340
| | | | llvm-svn: 333766
* [DAG] Simplify Expression. NFC.Nirav Dave2018-06-011-9/+3
| | | | llvm-svn: 333765
* [DAG] Remove untriggerable check. NFCI.Nirav Dave2018-06-011-10/+0
| | | | | | Candidate check precludes this check. llvm-svn: 333764
* [DAG] Prune store merge legal store check to stop invalid size. NFCI.Nirav Dave2018-06-011-0/+15
| | | | | | Do not consider store sizes large than the maximum legal store size. llvm-svn: 333763
* [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZKrzysztof Parzyszek2018-06-013-15/+80
| | | | llvm-svn: 333760
* [NFC] Zero initialize local variablesHiroshi Inoue2018-06-011-1/+1
| | | | | | This patch makes local variables zero initialized to avoid broken values in debug output. llvm-svn: 333754
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-016-14/+73
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-0111-59/+32
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [AArch64][GlobalISel] Zero-extend s1 values when returning.Amara Emerson2018-06-012-12/+7
| | | | | | | | | | | Before we were relying on the any extend of the s1 to s32, but for AAPCS we need to zero-extend it to at least s8. Fixes PR36719 Differential Revision: https://reviews.llvm.org/D47425 llvm-svn: 333747
* Revert r333740: IPSCCP] Use PredicateInfo to propagate facts from cmp.Florian Hahn2018-06-012-134/+10
| | | | | | This is breaking the clang-with-thin-lto-ubuntu bot. llvm-svn: 333745
* [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction.Sander de Smalen2018-06-012-0/+39
| | | | | | | | | | | | | Unpredicated copy of floating-point immediate value into SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47482 llvm-svn: 333744
* [mips] Guard more aliases correctly.Simon Dardis2018-06-012-48/+56
| | | | | | Also, duplicate an alias for microMIPS. llvm-svn: 333741
* Recommit r333268: [IPSCCP] Use PredicateInfo to propagate facts from cmp ↵Florian Hahn2018-06-012-10/+134
| | | | | | | | | | | | | | | | | | | instructions. This patch updates IPSCCP to use PredicateInfo to propagate facts to true branches predicated by EQ and to false branches predicated by NE. As a follow up, we should be able to extend it to also propagate additional facts about nonnull. Reviewers: davide, mssimpso, dberlin, efriedma Reviewed By: davide, dberlin Differential Revision: https://reviews.llvm.org/D45330 llvm-svn: 333740
* [mips] Guard 'nop' properly and add mips16's nop instructionSimon Dardis2018-06-013-12/+19
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47583 llvm-svn: 333739
* DWARFAcceleratorTable: Add an iterator-based api for accessing names in the ↵Pavel Labath2018-06-012-37/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | index Summary: Back when we were introducing the DWARF v5 name index, there was a short discussion whether we shouldn't have a nicer api for iterating over the index. At that time, I did not find it necessary since the iteration over names was done only from within the index itself (and I figured the internal implementation can deal with a slightly rough interface). However, now I ran into a use for this kind of API in LLDB (for finding all names matching a regular expression), so it looked like a nice opportunity to introduce one. To make the API more useful, I've made the NameTableEntry class a bit smarter: it now stores the string section reference (so it can return its name) and its position in the name index (mainly useful for dumping/logging). I also convert the internal users to use the new API, which also gives test coverage for the added code. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47590 llvm-svn: 333738
* [mips] Select the correct instruction for computing frameindexesSimon Dardis2018-06-014-3/+7
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47582 llvm-svn: 333736
* NFC Avoid a warning in WasmEHPrepare.cppGabor Buella2018-06-011-1/+1
| | | | | | | | | | ``` ../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic] false, false); ^ ``` llvm-svn: 333732
* [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction.Sander de Smalen2018-06-017-1/+137
| | | | | | | | | | | | | Unpredicated copy of repeating immediate pattern to SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47328 llvm-svn: 333731
* [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg ↵Craig Topper2018-06-011-7/+18
| | | | | | | | encodes a GPR. This is different than the behavior of EVEX.X extending modrm.rm to 5 bits. llvm-svn: 333728
* [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when ↵Craig Topper2018-06-011-0/+1
| | | | | | modrm.rm encodes a k-register. llvm-svn: 333727
* [X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.Craig Topper2018-06-011-3/+4
| | | | | | A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR. llvm-svn: 333725
* [X86][Disassembler] Make sure EVEX.X is not used to extend base registers of ↵Craig Topper2018-06-011-3/+5
| | | | | | | | | | memory operations. This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3. I think there are still more bugs related to this. llvm-svn: 333722
* [X86][Disassembler] Use a local variable instead of using a field in the ↵Craig Topper2018-06-012-10/+11
| | | | | | instruction object. NFC llvm-svn: 333721
* AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.tdTom Stellard2018-06-013-70/+6
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D47487 llvm-svn: 333720
* [X86] Make sure the check for VEX.vvvv being all ones on instructions that ↵Craig Topper2018-06-011-1/+3
| | | | | | don't use it doesn't ignore a bit in 32-bit mode. llvm-svn: 333717
* [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.Craig Topper2018-06-011-2/+2
| | | | llvm-svn: 333714
* Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.Heejin Ahn2018-06-014-48/+51
| | | | | | | | | | | | | | | | | | Summary: `getEHScopeMembership()` function is used not only for funclet-based EHs; they apply to all EH schemes that use the scoped IR (catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of the term 'funclet' to 'EH scopes' in case they apply to all scoped EH, and this fixes more of them. For `FuncletLayout` pass, I left it as is because the pass is only used for funclet-based EH. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47611 llvm-svn: 333711
* [WebAssembly] Update to the new names for the memory intrinsics.Dan Gohman2018-05-311-0/+9
| | | | | | | | | The WebAssembly committee has decided on the names `memory.size` and `memory.grow` for the memory intrinsics, so update the LLVM intrinsics to follow those names, keeping both sets of old names in place for compatibility. llvm-svn: 333708
* [WebAssembly] Fix the signatures for the __mulo* libcalls.Dan Gohman2018-05-311-3/+31
| | | | | | | | The __mulo* libcalls have an extra i32* to return the overflow value. Fixes PR37401. llvm-svn: 333706
* [WebAssembly] Support instruction selection for catching exceptionsHeejin Ahn2018-05-3112-14/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This lowers exception catching-related instructions: 1. Lowers `wasm.catch` intrinsic to `catch` instruction 2. Removes `catchpad` and `cleanuppad` instructions; they are not necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or `MachineBasicBlock::isEHPad()` can be used instead.) 3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret` and `cleanupret` instructions in isel, which will be replaced with other instructions in `WebAssemblyExceptionPrepare` pass. 4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various transformation for EH. Currently this pass only replaces `catchret` and `cleanupret` instructions into appropriate wasm instructions to make this patch successfully run until the end. Currently this does not handle lowering of intrinsics related to LSDA info generation (`wasm.landingpad.index` and `wasm.lsda`), because they cannot be tested without implementing `EHStreamer`'s wasm-specific handlers. They are marked as TODO, which is needed to make isel pass. Also this does not generate `try` and `end_try` markers yet, which will be handled in later patches. This patch is based on the first wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D44090 llvm-svn: 333705
* [LoopIdiomRecognize] Only convert loops to ctlz if we can prove that the ↵Craig Topper2018-05-311-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | input is non-negative. Summary: Loop idiom recognize tries to convert loops like ``` int foo(int x) { int cnt = 0; while (x) { x >>= 1; ++cnt; } return cnt; } ``` into calls to ctlz, but if x is initially negative this loop should be infinite. It happens that the cases that motivated this change have an absolute value of x before the loop. So this patch restricts the transform to cases where we know x is positive. Note: We are relying on the absolute value of INT_MIN to be undefined so we can assume that the result is always positive. Fixes PR37479 Reviewers: spatel, hfinkel, efriedma, javed.absar Reviewed By: efriedma Subscribers: dmgreen, llvm-commits Differential Revision: https://reviews.llvm.org/D47348 llvm-svn: 333702
* [WebAssembly] Add Wasm exception handling prepare passHeejin Ahn2018-05-315-6/+358
| | | | | | | | | | | | | | | | Summary: This adds a pass that transforms a program to be prepared for Wasm exception handling. This is using Windows EH instructions and based on the previous Wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, mgorny, sbc100, jgravelle-google, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D43746 llvm-svn: 333696
* [AMDGPU] Construct memory clauses before RAStanislav Mekhanoshin2018-05-315-0/+422
| | | | | | | | | | | | | | | | | | Memory clauses are formed into bundles in presence of xnack. Their source operands are marked as early-clobber. This allows to allocate distinct source and destination registers within a clause and prevent breaking the clause with s_nop in the hazard recognizer. Clauses are undone before post-RA scheduler to allow some rescheduling, which will not break the clause since artificial edges are created in the dag to keep memory operations together. Yet this allows a better ILP in some cases. Differential Revision: https://reviews.llvm.org/D47511 llvm-svn: 333691
* [InstCombine] narrow select to match condition operands' sizeSanjay Patel2018-05-311-8/+11
| | | | | | | | | | | | | This is the planned enhancement to D47163 / rL333611. We want to match cmp/select sizes because that will be recognized as min/max more easily and lead to better codegen (especially for vector types). As mentioned in D47163, this improves some of the tests that would also be folded by D46380, so we may want to adjust that patch to match the new patterns where the extend op occurs after the select. llvm-svn: 333689
* [ORC] Add a getRequestedSymbols method to MaterializationResponsibility.Lang Hames2018-05-311-7/+37
| | | | | | | | | | | This method returns the set of symbols in the target VSO that have queries waiting on them. This can be used to make decisions about which symbols to delegate to another MaterializationUnit (typically this will involve delegating all symbols that have *not* been requested to another MaterializationUnit so that materialization of those symbols can be deferred until they are requested). llvm-svn: 333684
* [ORC] Rename IRMaterializationUnit's Discardable member to SymbolToDefinition,Lang Hames2018-05-311-4/+6
| | | | | | | | | | and make it protected rather than private. The new name reflects the actual information in the map, and this information can be useful to derived classes (for example, to quickly look up the IR definition of a requested symbol). llvm-svn: 333683
* IRGen: Write .dwo files when -split-dwarf-file is used together with ↵Peter Collingbourne2018-05-311-1/+6
| | | | | | | | -fthinlto-index. Differential Revision: https://reviews.llvm.org/D47597 llvm-svn: 333677
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