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* Revert r212572 "improve BasicAA CS-CS queries", it causes PR20303.Nick Lewycky2014-07-153-142/+126
| | | | llvm-svn: 213024
* [DAGCombiner] Avoid calling method 'isShuffleMaskLegal' on illegal vector types.Andrea Di Biagio2014-07-151-0/+2
| | | | | | | | | | | | | | | | | | This patch fixes a crasher in method 'DAGCombiner::visitOR' due to an invalid call to method 'isShuffleMaskLegal'. On x86, method 'isShuffleMaskLegal' always expects a legal vector value type in input. With this patch, we immediately check if the input OR dag node has a legal vector type; we only try to fold a OR dag node into a single shufflevector if we know that the resulting shuffle will have a legal type. This is to avoid calling method 'isShuffleMaskLegal' on a potentially illegal vector value type. Added a new test-case to file 'CodeGen/X86/combine-or.ll' to verify that DAGCombiner doesn't crash in the attempt to check/combine an OR between shuffles with illegal types. llvm-svn: 213020
* R600: Add denormal handling subtarget features.Matt Arsenault2014-07-145-4/+56
| | | | llvm-svn: 213018
* R600/SI: Default to no single precision denormals.Matt Arsenault2014-07-141-1/+9
| | | | llvm-svn: 213017
* [RuntimeDyld] Handle endiannes differences between the host and target whileLang Hames2014-07-141-14/+19
| | | | | | | | | | reading MachO files magic numbers in RuntimeDyld. This is required now that we're testing cross-platform JITing (via RuntimeDyldChecker), and should fix some issues that David Fang has seen on PPC builds. llvm-svn: 213012
* [X86] Specify all TSFlags bit-offsets symbolicallyAdam Nemet2014-07-141-3/+6
| | | | | | | | | | | | | | | No functional change. The offsets for the other bitfields are specified symbolically. I need to increase the size for one of the earlier fields which is easier after this cleanup. Why these bits are relative to VEXShift is a bit strange but that is for another cleanup. I made sure that the values for the enums are unchanged after this change. llvm-svn: 213011
* CodeGen: Stick constant pool entries in COMDAT sections for WinCOFFDavid Majnemer2014-07-1411-16/+127
| | | | | | | | | | | | | | | | COFF lacks a feature that other object file formats support: mergeable sections. To work around this, MSVC sticks constant pool entries in special COMDAT sections so that each constant is in it's own section. This permits unused constants to be dropped and it also allows duplicate constants in different translation units to get merged together. This fixes PR20262. Differential Revision: http://reviews.llvm.org/D4482 llvm-svn: 213006
* Fix a -Wunused-local-typedefs warningAlp Toker2014-07-141-1/+1
| | | | llvm-svn: 213002
* [DAGCombiner] Add more rules to combine shuffle vector dag nodes.Andrea Di Biagio2014-07-141-0/+44
| | | | | | | | | | | | | | | | This patch teaches the DAGCombiner how to fold a pair of shuffles according to rules: 1. shuffle(shuffle A, B, M0), B, M1) -> shuffle(A, B, M2) 2. shuffle(shuffle A, B, M0), A, M1) -> shuffle(A, B, M3) The new rules would only trigger if the resulting shuffle has legal type and legal mask. Added test 'combine-vec-shuffle-3.ll' to verify that DAGCombiner correctly folds shuffles on x86 when the resulting mask is legal. Also added some negative cases to verify that we avoid introducing illegal shuffles. llvm-svn: 213001
* Look through addrspacecast in IsConstantOffsetFromGlobalMatt Arsenault2014-07-141-1/+2
| | | | llvm-svn: 213000
* Look through addrspacecast in GetPointerBaseWithConstantOffsetMatt Arsenault2014-07-141-1/+2
| | | | llvm-svn: 212999
* CodeGen: Add a getSectionKind method to MachineConstantPoolEntryDavid Majnemer2014-07-142-15/+32
| | | | | | This is just a helper routine, no functionality has changed. llvm-svn: 212993
* InstSimplify: Correct sdiv x / -1David Majnemer2014-07-141-11/+13
| | | | | | | | | | | Determining the bounds of x/ -1 would start off with us dividing it by INT_MIN. Suffice to say, this would not work very well. Instead, handle it upfront by checking for -1 and mapping it to the range: [INT_MIN + 1, INT_MAX. This means that the result of our division can be any value other than INT_MIN. llvm-svn: 212981
* InstSimplify: The upper bound of X / C was missing a rounding stepDavid Majnemer2014-07-141-1/+9
| | | | | | | | | | | | | | | | | | Summary: When calculating the upper bound of X / -8589934592, we would perform the following calculation: Floor[INT_MAX / 8589934592] However, flooring the result would make us wrongly come to the conclusion that 1073741824 was not in the set of possible values. Instead, use the ceiling of the result. Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4502 llvm-svn: 212976
* Support: Use a range-based forJustin Bogner2014-07-141-5/+4
| | | | llvm-svn: 212973
* Look through addrspacecast when checking isDereferenceablePointerMatt Arsenault2014-07-141-0/+3
| | | | llvm-svn: 212971
* Don't eliminate memcpy's when the address of the pointer may itself be ↵Nick Lewycky2014-07-141-0/+6
| | | | | | relevant. Fixes PR18304. Patch by David Wiberg! llvm-svn: 212970
* Unify the lowering of arguments during SjLj prepare.Bill Wendling2014-07-141-28/+10
| | | | | | | The 'select true, %arg, undef' instruction can be used for both aggregate and non-aggregate arguments. llvm-svn: 212967
* fixed typoSanjay Patel2014-07-141-1/+1
| | | | llvm-svn: 212966
* Use pointer type cast helpers.Matt Arsenault2014-07-141-3/+2
| | | | llvm-svn: 212963
* Add CreatePointerBitCastOrAddrSpaceCast to IRBuilder and co.Matt Arsenault2014-07-141-8/+26
| | | | llvm-svn: 212962
* X86: correct 64-bit atomics on 32-bitSaleem Abdulrasool2014-07-141-12/+8
| | | | | | | | | | | | | | | | We would emit a libcall for a 64-bit atomic on x86 after SVN r212119. This was due to the misuse of hasCmpxchg16 to indicate if cmpxchg8b was supported on a 32-bit target. They were added at different times and would result in the border condition being mishandled. This fixes the border case to emit the cmpxchg8b instruction for 64-bit atomic operations on x86 at the cost of restoring a long-standing bug in the codegen. We emit a cmpxchg8b on all x86 targets even where the CPU does not support this instruction (pre-Pentium CPUs). Although this bug should be fixed, this was present prior to SVN r212119 and this change, so this is not really introducing a regression. llvm-svn: 212956
* CodeGen: add missing includeSaleem Abdulrasool2014-07-141-0/+1
| | | | | | | Found during windows unwinding work. This header is indirectly included through a chain leading through Support/Win64EH.h. Explicitly include the header. NFC. llvm-svn: 212955
* X86: remove temporary atomicrmw used during lowering.Tim Northover2014-07-141-2/+5
| | | | | | | | | | | We construct a temporary "atomicrmw xchg" instruction when lowering atomic stores for widths that aren't supported natively. This isn't on the top-level worklist though, so it won't be removed automatically and we have to do it ourselves once that itself has been lowered. Thanks Saleem for pointing this out! llvm-svn: 212948
* Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, ↵Daniel Sanders2014-07-141-5/+23
| | | | | | | | .data, .reginfo, .MIPS.options, and .MIPS.abiflags The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly. llvm-svn: 212946
* Revert: [mips] Correct section alignments and EntrySizes for .bss, .text, ↵Daniel Sanders2014-07-141-23/+5
| | | | | | | | .data, .reginfo, .MIPS.options, and .MIPS.abiflags This commit causes multiple lld tests to fail. Reverting while I investigate the issue. llvm-svn: 212945
* [mips] Correct section alignments and EntrySizes for .bss, .text, .data, ↵Daniel Sanders2014-07-141-5/+23
| | | | | | | | | | | | | | | | | | .reginfo, .MIPS.options, and .MIPS.abiflags Summary: .bss, .text, and .data are at least 16-byte aligned. .reginfo is 4-byte aligned and has a 24-byte EntrySize. .MIPS.abiflags has an 24-byte EntrySize. .MIPS.options is 8-byte aligned and has 1-byte EntrySize. Using a 1-byte EntrySize for .MIPS.options seems strange because the records are neither 1-byte long nor fixed-length but this matches the value that GAS emits. Differential Revision: http://reviews.llvm.org/D4487 llvm-svn: 212939
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use ↵Daniel Sanders2014-07-145-23/+119
| | | | | | | | | | | | | | | | | | | | | mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
* [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-07-143-25/+13
| | | | | | | | | | | | | | FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
* AArch64: remove unnecessary pseudo-instruction.Tim Northover2014-07-142-15/+3
| | | | | | | Sufficiently twisted use of TableGen lets us write patterns directly for f16 (as an i16 promoted to i32) -> f32 conversion. llvm-svn: 212933
* [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no ↵Daniel Sanders2014-07-142-3/+4
| | | | | | | | '.module oddspreg' is used Differential Revision: http://reviews.llvm.org/D4486 llvm-svn: 212932
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-146-12/+84
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* Support lowering of empty aggregates.Bill Wendling2014-07-141-11/+11
| | | | | | | | | | | | | This crash was pretty common while compiling Rust for iOS (armv7). Reason - SjLj preparation step was lowering aggregate arguments as ExtractValue + InsertValue. ExtractValue has assertion which checks that there is some data in value, which is not true in case of empty (no fields) structures. Rust uses them quite extensively so this patch uses a 'select true, %val, undef' instruction to lower the argument. Patch by Valerii Hiora. llvm-svn: 212922
* NVPTX/LLVMBuild.txt: Add "Scalar" to required_libraries. It is really ↵NAKAMURA Takumi2014-07-141-1/+1
| | | | | | referenced. llvm-svn: 212918
* Object/LLVMBuild.txt: Sort required_libraries by alphabetical order.NAKAMURA Takumi2014-07-141-1/+1
| | | | llvm-svn: 212917
* [DAGCombiner] Fix a crash caused by a missing check for legal type when ↵Andrea Di Biagio2014-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | trying to fold shuffles. Verify that DAGCombiner does not crash when trying to fold a pair of shuffles according to rule (added at r212539): (shuffle (shuffle A, Undef, M0), Undef, M1) -> (shuffle A, Undef, M2) The DAGCombiner avoids folding shuffles if the resulting shuffle dag node is not legal for the target. That means, the resulting shuffle must have legal type and legal mask. Before, the DAGCombiner only called method 'TargetLowering::isShuffleMaskLegal' to check if it was "safe" to fold according to the above-mentioned rule. However, this caused a crash in the x86 backend since method 'isShuffleMaskLegal' always expects to be called on a legal vector type. llvm-svn: 212915
* MC: make MCWin64EHInstruction a POD-like structSaleem Abdulrasool2014-07-131-29/+28
| | | | | | | | | | | | | | | | This is the first of a number of changes designed to generalise MCWin64EHInstruction to support different target architectures. An ordered set (vector) of these instructions is saved per frame to permit the emission of information for Windows NT style unwinding. The only bit of information which is actually target specific here is the Opcode for the unwinding bytecode. The remainder of the information is simply generic information that is relevant to the Windows NT unwinding model. Remove the accessors for the fields, making them const and public instead. Sink the knowledge of the alias'ed name into the single source and sink a single-use check method into the use. llvm-svn: 212914
* MC: make helper function be more const-correctSaleem Abdulrasool2014-07-131-10/+7
| | | | | | | Introduce const-ness on parameters, they are used as read-only and should not be modified. NFC. llvm-svn: 212913
* MC: make DWARF and Windows unwinding handling more similarSaleem Abdulrasool2014-07-135-99/+95
| | | | | | | | Rename member variables and functions for the MCStreamer for DWARF-like unwinding management. Rename the Windows ones as well and make the naming and handling similar across the two. No functional change intended. llvm-svn: 212912
* Add forgotten `break` statement.Simon Atanasyan2014-07-131-0/+1
| | | | llvm-svn: 212910
* [Mips] Support SHT_MIPS_ABIFLAGS section type flag in the llvm-readobj,Simon Atanasyan2014-07-131-0/+1
| | | | | | obj2yaml and yaml2obj tools. llvm-svn: 212908
* [CMake] Add LLVM_LINK_COMPONENTS to loadable modules, LLVMHello and ↵NAKAMURA Takumi2014-07-131-0/+4
| | | | | | BugpointPasses, on Win32. llvm-svn: 212904
* IR: Allow comdats to be applied to globals with internal linkageDavid Majnemer2014-07-131-4/+3
| | | | | | | | | | Our verifier check for checking if a global has local linkage was too strict. Forbid private linkage but permit local linkage. Object file formats permit this and forbidding it prevents elimination of unused, internal, vftables under the MSVC ABI. llvm-svn: 212900
* MC: Let non-temporary COFF aliases be in symtabDavid Majnemer2014-07-131-8/+19
| | | | | | | | | | | | | | MC was aping a binutils bug where aliases would default their linkage to private instead of internal. I've sent a patch to the binutils maintainers and they've recently applied it to the GNU assembler sources. This fixes PR20152. Differential Revision: http://reviews.llvm.org/D4395 llvm-svn: 212899
* Remove unused includeMatt Arsenault2014-07-131-1/+0
| | | | llvm-svn: 212898
* R600: Use range for and fix missing consts.Matt Arsenault2014-07-132-29/+20
| | | | llvm-svn: 212897
* R600: Make ShaderType privateMatt Arsenault2014-07-139-34/+45
| | | | llvm-svn: 212896
* R600: Add option to disable promote allocaMatt Arsenault2014-07-134-5/+24
| | | | | | | This can make writing some tests harder, so add a flag to disable it. llvm-svn: 212893
* Templatify DominanceFrontier.Matt Arsenault2014-07-123-109/+81
| | | | | | Theoretically this should now work for MachineBasicBlocks. llvm-svn: 212885
* AArch64: add support for llvm.aarch64.hint intrinsicSaleem Abdulrasool2014-07-121-11/+17
| | | | | | | | | | | This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to support the various hint intrinsic functions in the ACLE. Add an optional pattern field that permits the subclass to specify the pattern that matches the selection. The intrinsic pattern is set as mayLoad, mayStore, so overload the value for the definition of the hint instruction. llvm-svn: 212883
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