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* [AVX-512] Add VPABSB/D/Q/W to load folding tables.Craig Topper2017-02-061-0/+34
| | | | llvm-svn: 294169
* [AVX-512] Add VSHUFPS/PD to load folding tables.Craig Topper2017-02-061-0/+16
| | | | llvm-svn: 294168
* [AVX-512] Add VPMULLD/Q/W instructions to load folding tables.Craig Topper2017-02-061-0/+27
| | | | llvm-svn: 294164
* [AVX-512] Add all masked and unmasked versions of VPMULDQ and VPMULUDQ to ↵Craig Topper2017-02-051-0/+16
| | | | | | load folding tables. llvm-svn: 294163
* [X86][SSE] Replace insert_vector_elt(vec, -1, idx) with shuffleSimon Pilgrim2017-02-051-8/+12
| | | | | | Similar to what we already do for zero elt insertion, we can quickly rematerialize 'allbits' vectors so to avoid a unnecessary gpr value and insertion into a vector llvm-svn: 294162
* [AVX-512] Add scalar masked max/min intrinsic instructions to the load ↵Craig Topper2017-02-051-0/+12
| | | | | | folding tables. llvm-svn: 294153
* [AVX-512] Add scalar masked add/sub/mul/div intrinsic instructions to the ↵Craig Topper2017-02-051-0/+24
| | | | | | load folding tables. llvm-svn: 294152
* [AVX-512] Add masked scalar FMA intrinsics to ↵Craig Topper2017-02-051-0/+24
| | | | | | isNonFoldablePartialRegisterLoad to improve load folding of scalar loads. llvm-svn: 294151
* [AVR] Implement stacksave/stackrestore by expanding (PR31342)Dylan McKay2017-02-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Authored by Florian Zeitz. This implements the missing stacksave/stackrestore intrinsics via expansion. Output of `llc -O0 -march=avr ~/devel/llvm/test/CodeGen/Generic/stacksave-restore.ll` for sanity checking (comments mine): ``` .text .file ".../llvm/test/CodeGen/Generic/stacksave-restore.ll" .globl test .p2align 1 .type test,@function test: ; @test ; BB#0: push r28 push r29 in r28, 61 in r29, 62 sbiw r28, 4 in r0, 63 cli out 62, r29 out 63, r0 out 61, r28 in r18, 61 in r19, 62 mov r20, r22 mov r21, r23 in r30, 61 in r31, 62 lsl r22 rol r23 lsl r22 rol r23 in r26, 61 in r27, 62 sub r26, r22 sbc r27, r23 andi r26, 252 in r0, 63 cli out 62, r27 out 63, r0 out 61, r26 in r0, 63 cli out 62, r31 out 63, r0 out 61, r30 in r30, 61 in r31, 62 sub r30, r22 sbc r31, r23 andi r30, 252 in r0, 63 cli out 62, r31 out 63, r0 out 61, r30 std Y+3, r24 ; 2-byte Folded Spill std Y+4, r25 ; 2-byte Folded Spill mov r24, r26 mov r25, r27 in r0, 63 cli out 62, r19 out 63, r0 out 61, r18 std Y+1, r20 ; 2-byte Folded Spill std Y+2, r21 ; 2-byte Folded Spill adiw r28, 4 in r0, 63 cli out 62, r29 out 63, r0 out 61, r28 pop r29 pop r28 ret .Lfunc_end0: .size test, .Lfunc_end0-test ``` Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29553 llvm-svn: 294146
* Revamp llvm::once_flag to be closer to std::once_flagKamil Rytarowski2017-02-053-3/+3
| | | | | | | | | | | | | | | | | | | Summary: Make this interface reusable similarly to std::call_once and std::once_flag interface. This makes porting LLDB to NetBSD easier as there was in the original approach a portable way to specify a non-static once_flag. With this change translating std::once_flag to llvm::once_flag is mechanical. Sponsored by <The NetBSD Foundation> Reviewers: mehdi_amini, labath, joerg Reviewed By: mehdi_amini Subscribers: emaste, clayborg Differential Revision: https://reviews.llvm.org/D29566 llvm-svn: 294143
* [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.Craig Topper2017-02-051-6/+10
| | | | llvm-svn: 294132
* [X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit ↵Craig Topper2017-02-051-14/+14
| | | | | | %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
* [X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly ↵Craig Topper2017-02-051-25/+13
| | | | | | | | | | | | creating a PSHUFB. This will be lowered by regular shuffle lowering to a PSHUFB later. Similar was already done for several other shuffles in this function. The test changes are because the old code used explicity zeroing for elements that could have been undef. While I was here I also changed other shuffle vectors in the same function to use the same input twice instead of creating UNDEF nodes. getVectorShuffle can create the UNDEF for us. llvm-svn: 294130
* [SelectionDAG] In InstrEmitter, handle EXTRACT_SUBREG of a physical register.Geoff Berry2017-02-051-8/+23
| | | | | | | | | | | | | | | | | | | Summary: Without this change, the getVR() call would hit an assert since it was being passed a physical register. Update the AArch64/ldst-opt.ll test with a case that triggers this behavior by adding a run with strict-align, which causes an unaligned STR XZR instruction to be split into byte stores, creating an EXTRACT_SUBREG of XZR that triggers the original problem. Reviewers: bogner, qcolombet, MatzeB, atrick Subscribers: aemerson, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D29495 llvm-svn: 294129
* [DAGCombiner] Leverage add's commutativityAmaury Sechet2017-02-051-6/+14
| | | | | | | | | | | | Summary: This avoid the need to duplicate all pattern and actually end up exposing some opportunity to optimize existing pattern that did not exists in both directions on an existing test case. Reviewers: mkuper, spatel, bkramer, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29541 llvm-svn: 294125
* [globalisel][arm] Tablegen-erate current Register Bank Information.Daniel Sanders2017-02-055-38/+27
| | | | | | | | | | | | | | | | | | Summary: This patch tablegen-erates the ARM register bank information so that the static tables added in D27807 no longer need to be maintained. Depends on D27338 Reviewers: t.p.northover, rovka, ab, qcolombet, aditya_nandakumar Reviewed By: rovka Subscribers: aemerson, rengolin, mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D28567 llvm-svn: 294124
* [AVR] Fix a bug where asm operands are printed twiceDylan McKay2017-02-051-1/+2
| | | | | | | We would unconditionally call printOperand, even if PrintAsmOperand already printed the immediate. llvm-svn: 294121
* [AVR] Support zero-sized arguments in defined methodsDylan McKay2017-02-051-0/+6
| | | | | | | | | | | It is sufficient to skip emission of these arguments as we have nothing to actually pass through the function call. The AVR-GCC reference has nothing to say about zero-sized arguments, presumably because C/C++ doesn't support them. This means we don't have to worry about ABI differences. llvm-svn: 294119
* Refactor SampleProfile.cpp to make it cleaner. (NFC)Dehao Chen2017-02-051-32/+14
| | | | llvm-svn: 294118
* [X86] Add support for folding (insert_subvector vec1, (extract_subvector ↵Craig Topper2017-02-041-2/+25
| | | | | | vec2, idx1), idx1) -> (blendi vec2, vec1). llvm-svn: 294112
* [X86] Simplify the code that turns INSERT_SUBVECTOR into BLENDI. NFCICraig Topper2017-02-041-19/+8
| | | | llvm-svn: 294111
* [DAGCombiner] Canonicalize the order of a chain of INSERT_SUBVECTORs.Craig Topper2017-02-041-4/+24
| | | | | | Based on similar code for INSERT_VECTOR_ELT. llvm-svn: 294110
* [DAGCombiner] Use DAG.getAnyExtOrTrunc to simplify some code. NFCCraig Topper2017-02-041-5/+1
| | | | llvm-svn: 294109
* [DAGCombiner] In visitINSERT_VECTOR_ELT, move check for BUILD_VECTOR being ↵Craig Topper2017-02-041-4/+4
| | | | | | legal below code that just canonicalizes INSERT_VECTOR_ELT without creating BUILD_VECTORS. llvm-svn: 294108
* [IPCP] Don't propagate return value for naked functions.Davide Italiano2017-02-041-1/+7
| | | | | | This is pretty much the same change made in SCCP. llvm-svn: 294098
* Formatting in DAGCombiner. NFCAmaury Sechet2017-02-041-0/+2
| | | | llvm-svn: 294091
* Fix variable name /NFCXinliang David Li2017-02-041-2/+2
| | | | llvm-svn: 294090
* MachineCopyPropagation: Respect implicit operands of COPYMatthias Braun2017-02-041-17/+31
| | | | | | | | | The code missed to check implicit operands of COPY instructions for defs/uses. Differential Revision: https://reviews.llvm.org/D29522 llvm-svn: 294088
* MachineCopyPropagation: Do not consider undef operands as clobbersMatthias Braun2017-02-041-8/+0
| | | | | | | | | | | | | | This was originally introduced in r278321 to work around correctness problems in the ExecutionDepsFix pass; Probably also to keep the performance benefits of breaking the false dependencies which of course also affect undef operands. ExecutionDepsFix has been improved here recently (see for example r278321) so we should not need this exception any longer. Differential Revision: https://reviews.llvm.org/D29525 llvm-svn: 294087
* [CodeGen]: BlockPlacement: Skip extraneous logging.Kyle Butt2017-02-041-3/+3
| | | | | | | Move a check for blocks that are not candidates for tail duplication up before the logging. Reduces logging noise. No non-logging changes intended. llvm-svn: 294086
* [CodeGen]: BlockPlacement: Apply const liberally. NFCKyle Butt2017-02-041-94/+103
| | | | | | | | Anything that needs to be passed to AnalyzeBranch unfortunately can't be const, or more would be const. Added const_iterator to BlockChain to allow BlockChain to be const when we don't expect to change it. llvm-svn: 294085
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-02-041-26/+62
| | | | | | | | other minor fixes (NFC). This is preparation to reduce TargetInstrInfo.h dependencies. llvm-svn: 294084
* [TwoAddressInstruction] Fix typo in comment. NFCCraig Topper2017-02-041-1/+1
| | | | llvm-svn: 294083
* Remove a bunch of unnecessary casts to a target specific version of TII and ↵Eric Christopher2017-02-041-26/+13
| | | | | | TRI as we're working from a target specific STI. llvm-svn: 294081
* fix nullptr Mangler in LTOModuleBob Haarman2017-02-041-2/+7
| | | | | | | | | | Reviewers: kcc, pcc Subscribers: mehdi_amini Differential Revision: https://reviews.llvm.org/D29523 llvm-svn: 294079
* [Sparc] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-042-36/+57
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294072
* [RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUEBrendon Cahoon2017-02-041-1/+1
| | | | | | | | | | | An assert occurs when calling SlotIndexes::getInstructionIndex with a DBG_VALUE instruction because the function expects an instruction with a slot index. However, there is no slot index for a DBG_VALUE instruction. Differential Revision: https://reviews.llvm.org/D29048 llvm-svn: 294070
* [Mips] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-034-8/+20
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294069
* [SystemZ] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-033-4/+31
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294068
* [AMDGPU] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-031-5/+9
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294067
* [InstCombine] treat i1 as a special type in shouldChangeType()Sanjay Patel2017-02-031-4/+8
| | | | | | | | | | | | | | | | | | | | This patch is based on the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2017-January/109631.html Folding to i1 should always be desirable because that's better for value tracking and we have special folds for i1 types. I checked for other users of shouldChangeType() where this might have an effect, but we already handle the i1 case differently than other types in all of those cases. Side note: the default datalayout includes i1, so it seems we only find this gap in shouldChangeType + phi folding for the case when there is (1) an explicit datalayout without i1, (2) casting to i1 from a legal type, and (3) a phi with exactly 2 incoming casted operands (as Björn mentioned). Differential Revision: https://reviews.llvm.org/D29336 llvm-svn: 294066
* [APInt] Add integer API bor bitwise operations.Amaury Sechet2017-02-031-0/+12
| | | | | | | | | | | | Summary: As per title. I ran into that limitation of the API doing some other work, so I though that'd be a nice addition. Reviewers: jroelofs, compnerd, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29503 llvm-svn: 294063
* [libFuzzer] properly hide the memcmp interceptor from msanKostya Serebryany2017-02-031-1/+1
| | | | llvm-svn: 294061
* [PGO] Add select instr profile in graph dumpXinliang David Li2017-02-031-3/+32
| | | | | | Differential Revision: http://reviews.llvm.org/D29474 llvm-svn: 294055
* [AArch64] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-034-25/+46
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294053
* [ARM] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-032-2/+9
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294052
* [XCore] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-032-3/+9
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294051
* [InstCombine] fix operand-complexity-based canonicalization (PR28296)Sanjay Patel2017-02-031-7/+15
| | | | | | | | | | | | | | | | | | | The code comments didn't match the code logic, and we didn't actually distinguish the fake unary (not/neg/fneg) operators from arguments. Adding another level to the weighting scheme provides more structure and can help simplify the pattern matching in InstCombine and other places. I fixed regressions that would have shown up from this change in: rL290067 rL290127 But that doesn't mean there are no pattern-matching logic holes left; some combines may just be missing regression tests. Should fix: https://llvm.org/bugs/show_bug.cgi?id=28296 Differential Revision: https://reviews.llvm.org/D27933 llvm-svn: 294049
* Properly parse the TypeServer2 record.Zachary Turner2017-02-036-25/+57
| | | | llvm-svn: 294046
* AMDGPU: AsmParser cleanupsMatt Arsenault2017-02-031-17/+24
| | | | | | Use typedef, remove unnecessary enum, line wraps. llvm-svn: 294039
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