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* Clarify comments.Eric Christopher2013-07-141-4/+1
| | | | llvm-svn: 186297
* Add DW_AT_GNU_odr_signature to the set of dwarf attributes.Eric Christopher2013-07-141-0/+1
| | | | llvm-svn: 186296
* Collapse temporary variable into call.Eric Christopher2013-07-141-4/+2
| | | | llvm-svn: 186295
* Use conventional syntax for branches.Anton Korobeynikov2013-07-141-2/+2
| | | | | | Patch by Job! llvm-svn: 186291
* Properly lower jump tables on MSP430. Patch by Job Noorman!Anton Korobeynikov2013-07-141-2/+2
| | | | llvm-svn: 186283
* SLPVectorizer: change the order in which we search for vectorization ↵Nadav Rotem2013-07-141-4/+4
| | | | | | candidates. Do stores first and PHIs second. llvm-svn: 186277
* Fix build by replacing '>>' with '> >'Tobias Grosser2013-07-141-7/+5
| | | | llvm-svn: 186276
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-1455-214/+219
| | | | | | size. llvm-svn: 186274
* Remove a bunch of old SCEVExpander FIXME's for preserving NoWrap.Andrew Trick2013-07-141-17/+11
| | | | | | | | | | | | | | | The great thing about the SCEVAddRec No-Wrap flag (unlike nsw/nuw) is that is can be preserved while normalizing (reassociating and factoring). The bad thing is that is can't be tranfered back to IR, which is one of the reasons I don't like the concept of SCEVExpander. Sorry, I can't think of a direct way to test this, which is why these were FIXMEs for so long. I just think it's a good time to finally clean it up. llvm-svn: 186273
* Teach indvars to generate nsw/nuw flags when widening an induction variable.Andrew Trick2013-07-141-1/+6
| | | | | | Fixes PR16600. llvm-svn: 186272
* LoopVectorizer: Disallow reductions whose header phi is used outside the loopArnold Schwaighofer2013-07-131-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an outside loop user of the reduction value uses the header phi node we cannot just reduce the vectorized phi value in the vector code epilog because we would loose VF-1 reductions. lp: p = phi (0, lv) lv = lv + 1 ... brcond , lp, outside outside: usr = add 0, p (Say the loop iterates two times, the value of p coming out of the loop is one). We cannot just transform this to: vlp: p = phi (<0,0>, lv) lv = lv + <1,1> .. brcond , lp, outside outside: p_reduced = p[0] + [1]; usr = add 0, p_reduced (Because the original loop iterated two times the vectorized loop would iterate one time, but p_reduced ends up being zero instead of one). We would have to execute VF-1 iterations in the scalar remainder loop in such cases. For now, just disable vectorization. PR16522 llvm-svn: 186256
* Reduce large list of macros to the primary platform macros. DistingiushJoerg Sonnenberger2013-07-131-20/+18
| | | | | | | between ELF (Linux, FreeBSD, NetBSD) and OSX as platform for the assembler dialect. llvm-svn: 186252
* Pass SmallVector by const reference instead of by value.Craig Topper2013-07-131-2/+2
| | | | llvm-svn: 186243
* LoopVectorize fix: LoopInfo must be valid when invoking utils like SCEVExpander.Andrew Trick2013-07-131-18/+18
| | | | | | | | | | | In general, one should always complete CFG modifications first, update CFG-based analyses, like Dominatores and LoopInfo, then generate instruction sequences. LoopVectorizer was creating a new loop, calling SCEVExpander to generate checks, then updating LoopInfo. I just changed the order. llvm-svn: 186241
* Add a microoptimization for urem.Nick Lewycky2013-07-131-0/+7
| | | | llvm-svn: 186235
* Revert commit r186217 -- this is breaking bots:Chandler Carruth2013-07-131-19/+7
| | | | | | | | | | http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RAincremental/builds/4328 Original commit log: Use the function attributes to pass along the stack protector buffer size. llvm-svn: 186234
* Fix logic error optimizing "icmp pred (urem X, Y), Y" where pred is signed.Nick Lewycky2013-07-121-4/+7
| | | | | | Fixes PR16605. llvm-svn: 186229
* [mips] Implement MipsTargetMachine::getInstrItineraryData().Akira Hatanaka2013-07-123-2/+9
| | | | llvm-svn: 186227
* Fix ARM paired GPR COPY loweringJF Bastien2013-07-121-0/+3
| | | | | | | | | | | | | ARM paired GPR COPY was being lowered to two MOVr without CC. This patch puts the CC back. My test is a reduction of the case where I encountered the issue, 64-bit atomics use paired GPRs. The issue only occurs with selectionDAG, FastISel doesn't encounter it so I didn't bother calling it. llvm-svn: 186226
* Fix a crash in EvaluateInDifferentElementOrder where it would generate anJoey Gouly2013-07-121-1/+3
| | | | | | | | undef vector of the wrong type. LGTM'd by Nick Lewycky on IRC. llvm-svn: 186224
* [mips] Add instruction itinerary classes for mult, seb and slt instructions.Akira Hatanaka2013-07-123-13/+16
| | | | llvm-svn: 186222
* Use the function attributes to pass along the stack protector buffer size.Bill Wendling2013-07-121-7/+19
| | | | | | | Now that we have robust function attributes, don't use a command line option to specify the stack protecto buffer size. llvm-svn: 186217
* LFTR improvement to avoid truncation.Andrew Trick2013-07-121-6/+32
| | | | | | This is a reimplemntation of the patch originally in r186107. llvm-svn: 186215
* Cleanup LFTR logic.Andrew Trick2013-07-121-28/+9
| | | | llvm-svn: 186214
* Cleanup: rename a variable to make the logic easier to follow.Andrew Trick2013-07-121-7/+7
| | | | llvm-svn: 186213
* Remove extraneous braces.Eric Christopher2013-07-121-6/+3
| | | | llvm-svn: 186212
* Change llvm-ar to use lib/Object.Rafael Espindola2013-07-121-26/+23
| | | | | | | | | | | | | | | | | | | | | | This fixes two bugs is lib/Object that the use in llvm-ar found: * In OS X created archives, the name can be padded with nulls. Strip them. * In the constructor, remember the first non special member and use that in begin_children. This makes sure we skip all special members, not just the first one. The change to llvm-ar itself consist of * Using lib/Object for reading archives instead of ArchiveReader.cpp. * Writing the modified archive directly, instead of creating an in memory representation. The old Archive library was way more general than what is needed, as can be seen by the diffstat of this patch. Having llvm-ar using lib/Object now opens the way for creating regular symbol tables for both native objects and bitcode files so that we can use those archives for LTO. llvm-svn: 186197
* R600: Remove unsafe type punning. No intended functionality change.Benjamin Kramer2013-07-121-6/+4
| | | | llvm-svn: 186196
* X86 cost model: Add cost for vectorized gather/scatherArnold Schwaighofer2013-07-121-0/+15
| | | | | | radar://14351991 llvm-svn: 186189
* ARM cost model: Add cost for gather/scatherArnold Schwaighofer2013-07-121-0/+9
| | | | | | | | | | Fixes a 35% degradation compared to unvectorized code in MiBench/automotive-susan and an equally serious regression on a private image processing benchmark. radar://14351991 llvm-svn: 186188
* TargetTransformInfo: address calculation parameter for gather/scatherArnold Schwaighofer2013-07-124-8/+64
| | | | | | | | | | | Address calculation for gather/scather in vectorized code can incur a significant cost making vectorization unbeneficial. Add infrastructure to add cost. Tests and cost model for targets will be in follow-up commits. radar://14351991 llvm-svn: 186187
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-121-1/+1
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-6/+18
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-2/+6
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-122-3/+29
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-122-0/+19
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-123-1/+36
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-121-0/+35
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. llvm-svn: 186174
* X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when ↵Stephen Lin2013-07-121-0/+38
| | | | | | | | possible Patch by Andrea Di Biagio llvm-svn: 186165
* Don't reject an empty archive.Rafael Espindola2013-07-121-4/+6
| | | | llvm-svn: 186159
* Revert "indvars: Improve LFTR by eliminating truncation when comparingChandler Carruth2013-07-121-23/+4
| | | | | | | | | | | | | | | | | | | against a constant." This reverts commit r186107. It didn't handle wrapping arithmetic in the loop correctly and thus caused the following C program to count from 0 to UINT64_MAX instead of from 0 to 255 as intended: #include <stdio.h> int main() { unsigned char first = 0, last = 255; do { printf("%d\n", first); } while (first++ != last); } Full test case and instructions to reproduce with just the -indvars pass sent to the original review thread rather than to r186107's commit. llvm-svn: 186152
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-122-0/+49
| | | | | | cases are added. llvm-svn: 186151
* [SystemZ] Optimize sign-extends of vector setccsRichard Sandiford2013-07-121-0/+9
| | | | | | | | | | | | | Normal (sext (setcc ...)) sequences are optimised into (select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND. However, this is deliberately not done for vectors, and after vector type legalization we have (sext_inreg (setcc ...)) instead. I wondered about trying to extend DAGCombiner to handle this case too, but it seemed to be a loss on some other targets I tried, even those for which SETCC isn't "legal" and SELECT_CC is. llvm-svn: 186149
* [SystemZ] Fix parsing of inline asm registersRichard Sandiford2013-07-124-8/+49
| | | | | | | | | | | | GPR and FPR constraints like "{r2}" and "{f2}" weren't handled correctly because the name-to-regno mapping depends on the value type and (because of that) the internal names in RegStrings are not the same as the AsmName. CC constraints like "{cc}" didn't work either because there was no associated register class. llvm-svn: 186148
* [SystemZ] Improve spilling of LGDR and LDGRRichard Sandiford2013-07-121-1/+23
| | | | | | | If the source of these instructions is spilled we should load the destination. If the destination is spilled we should store the source. llvm-svn: 186147
* Stylistic change.Shuxin Yang2013-07-121-2/+2
| | | | | | Thank Nick for figuring out these problems. llvm-svn: 186146
* SLPVectorizer: Sink and enable CSE for ExtractElements.Nadav Rotem2013-07-121-11/+25
| | | | llvm-svn: 186145
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-128-26/+55
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* Windows/TimeValue.inc: Mute prefixed '0' on %d to emulate %e.NAKAMURA Takumi2013-07-121-0/+5
| | | | | | It fixes compatibility in llvm/test/Object/archive-toc.test. llvm-svn: 186142
* PEI: refactor replaceFrameIndices(MF) to call replaceFrameIndices(BB).Manman Ren2013-07-122-81/+87
| | | | | | | replaceFrameIndices(MF) will iterate over the BBs and call replaceFrameIndices(BB). No functionality change. llvm-svn: 186141
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