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* ArchV7M implies HW division instructions.Evan Cheng2010-08-111-3/+3
| | | | llvm-svn: 110797
* ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.Evan Cheng2010-08-111-11/+10
| | | | llvm-svn: 110796
* Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)Evan Cheng2010-08-112-32/+36
| | | | llvm-svn: 110795
* MC/ARM: Add basic support for handling predication by parsing it out of the ↵Daniel Dunbar2010-08-111-1/+44
| | | | | | mnemonic into a separate operand form. llvm-svn: 110794
* MC/ARM: Split mnemonic on '.' characters.Daniel Dunbar2010-08-111-3/+16
| | | | llvm-svn: 110793
* MC/ARM: Fill in ARMOperand::dump a bit.Daniel Dunbar2010-08-111-1/+21
| | | | llvm-svn: 110792
* llvm-mc: Add -show-inst-operands, for dumping the parsed instruction ↵Daniel Dunbar2010-08-112-1/+16
| | | | | | representation before matching. llvm-svn: 110791
* MCAsmParser: Add dump() hook to MCParsedAsmOperand.Daniel Dunbar2010-08-113-4/+4
| | | | llvm-svn: 110790
* MC/ARM: Add an ARMOperand class for condition codes.Daniel Dunbar2010-08-112-4/+30
| | | | llvm-svn: 110788
* Really control isel of barrier instructions with cpu feature.Evan Cheng2010-08-112-4/+4
| | | | llvm-svn: 110787
* Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng2010-08-111-0/+5
| | | | | | instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-117-55/+54
| | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
* MC/ARM: Switch to using the generated match functions instead of stub ↵Daniel Dunbar2010-08-111-81/+30
| | | | | | implementations. llvm-svn: 110783
* MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.Daniel Dunbar2010-08-112-2/+3
| | | | llvm-svn: 110782
* ARM: Mark some disassembler only instructions as not available for matching --Daniel Dunbar2010-08-111-0/+4
| | | | | | | for some reason they have a very odd MCInst form where the operands overlap, but I haven't dug in to find out why yet. llvm-svn: 110781
* ARM: Quote $p in an asm string.Daniel Dunbar2010-08-111-2/+2
| | | | llvm-svn: 110780
* Improve indentation.Owen Anderson2010-08-111-27/+28
| | | | llvm-svn: 110778
* Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.Bill Wendling2010-08-111-0/+5
| | | | llvm-svn: 110762
* Mark ARM compare instructions as isCompare.Bill Wendling2010-08-111-1/+1
| | | | llvm-svn: 110761
* When analyzing loop exit conditions combined with and and or, don'tDan Gohman2010-08-111-14/+12
| | | | | | | make any assumptions about when the two conditions will agree on when to permit the loop to exit. This fixes PR7845. llvm-svn: 110758
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-116-151/+179
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Rename and reorder the arguments to isImpliedCond, for consistency and clarity.Dan Gohman2010-08-101-10/+12
| | | | llvm-svn: 110750
* CBZ and CBNZ are implemented.Evan Cheng2010-08-101-5/+0
| | | | llvm-svn: 110745
* Add AVX matching patterns to Packed Bit Test intrinsics.Bruno Cardoso Lopes2010-08-104-33/+78
| | | | | | | | | | | | Apply the same approach of SSE4.1 ptest intrinsics but create a new x86 node "testp" since AVX introduces vtest{ps}{pd} instructions which set ZF and CF depending on sign bit AND and ANDN of packed floating-point sources. This is slightly different from what the "ptest" does. Tests comming with the other 256 intrinsics tests. llvm-svn: 110744
* Now that we're using ConstantRange to represent potential values, make use ↵Owen Anderson2010-08-101-8/+35
| | | | | | | | of that represenation to create constraints from comparisons other than eq/neq. llvm-svn: 110742
* Add the minimal amount of smarts necessary to instcombine of shufflevectors ↵Nate Begeman2010-08-101-64/+141
| | | | | | | | | | | | | | to recognize patterns generated by clang for transpose of a matrix in generic vectors. This is made of two parts: 1) Propagating vector extracts of hi/lo half into their users 2) Recognizing an insertion of even elements followed by the odd elements as an unpack. Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8. llvm-svn: 110734
* Turn optimize compares back on with fix. We needed to test that a machine op wasBill Wendling2010-08-102-2/+2
| | | | | | a register before checking if it was defined. llvm-svn: 110733
* Give up on register class recalculation when the register is used with subregJakob Stoklund Olesen2010-08-101-1/+10
| | | | | | | operands. We don't currently have a hook to provide "the largest super class of A where all registers' getSubReg(subidx) is valid and in B". llvm-svn: 110730
* Revert r110718; it broke clang-i386-darwin9.Dan Gohman2010-08-101-1/+1
| | | | llvm-svn: 110726
* Avoid editing the current live interval during remat.Jakob Stoklund Olesen2010-08-101-3/+3
| | | | | | | | The live interval may be used for a spill slot as well, and that spill slot could be shared by split registers. We cannot shrink it, even if we know the current register won't need the spill slot in that range. llvm-svn: 110721
* More debug spewJakob Stoklund Olesen2010-08-101-0/+2
| | | | llvm-svn: 110720
* Turn optimize cmps on by default so that we can get some testing by the nightlyBill Wendling2010-08-101-1/+1
| | | | | | ARM testers. llvm-svn: 110718
* Add missing argument. CreateCompositeTypeEx() users, please verify.Devang Patel2010-08-101-4/+5
| | | | llvm-svn: 110717
* Switch over to using ConstantRange to track integral values.Owen Anderson2010-08-101-7/+44
| | | | llvm-svn: 110714
* Do not forget debug info for enums. Use named mdnode to keep track of these ↵Devang Patel2010-08-102-2/+20
| | | | | | types. llvm-svn: 110712
* Delete some unused instructions.Evan Cheng2010-08-103-99/+0
| | | | llvm-svn: 110710
* Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng2010-08-105-63/+73
| | | | | | | | function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. llvm-svn: 110707
* Implement register class inflation.Jakob Stoklund Olesen2010-08-102-0/+42
| | | | | | | | | When splitting a live range, the new registers have fewer uses and the permissible register class may be less constrained. Recompute the register class constraint from the uses of new registers created for a split. This may let them be allocated from a larger set, possibly avoiding a spill. llvm-svn: 110703
* Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar2010-08-105-68/+63
| | | | | | register is", it breaks a couple test-suite tests. llvm-svn: 110701
* MC/AsmParser: Fix a bug in macro argument parsing, which was droppingDaniel Dunbar2010-08-101-5/+7
| | | | | | parentheses from argument lists. llvm-svn: 110692
* Recalculate the spill weight and allocation hint for virtual registers createdJakob Stoklund Olesen2010-08-102-2/+9
| | | | | | during live range splitting. llvm-svn: 110686
* Revert "MC/MachO: Fix possible null pointer dereference."Michael J. Spencer2010-08-101-1/+1
| | | | | | | | This reverts commit 110575. Target.isAbsolute() is true if SD would be null. llvm-svn: 110683
* Mark this variable as used.Chandler Carruth2010-08-101-0/+1
| | | | llvm-svn: 110667
* RegionInfo: Do not assert if a BB is not part of the dominance tree.Tobias Grosser2010-08-101-2/+4
| | | | llvm-svn: 110665
* Handle TAG_constant for integers.Devang Patel2010-08-102-22/+40
| | | | llvm-svn: 110656
* Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng2010-08-105-63/+68
| | | | | | | | | | reserved, not available for general allocation. This eliminates all the extra checks for Darwin. This change also fixes the use of FP to access frame indices in leaf functions and cleaned up some confusing code in epilogue emission. llvm-svn: 110655
* Update CMake...sorry for the breakage.Bill Wendling2010-08-101-2/+1
| | | | llvm-svn: 110654
* Simplify.Devang Patel2010-08-102-4/+4
| | | | llvm-svn: 110653
* Drop "const". It does not add value here.Devang Patel2010-08-102-10/+10
| | | | llvm-svn: 110652
* Add AVX movnt{pd,ps,dq} 256-bit intrinsicsBruno Cardoso Lopes2010-08-101-0/+7
| | | | llvm-svn: 110650
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