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* [X86] Remove SRAs from v16i8 multiply lowering on sse2 targetsCraig Topper2018-03-091-8/+10
| | | | | | | | | | Previously we unpacked the even bytes of each input into the high byte of 16-bit elements then did an v8i16 arithmetic shift right by 8 bits to fill the upper bits of each word with sign bits. Then we did the v8i16 multiply and then masked to zero the upper 8-bits of each result. The similar was done for all the odd bytes. The results are then packed together with packuswb Since we are masking each multiply result element to 8-bits, and those 8-bits are determined only by the lower 8-bits of each of the inputs, we don't need to fill the upper bits with sign bits. So we can just unpack into the low byte of each element and treat the upper bits as garbage. This is what gcc also does. Differential Revision: https://reviews.llvm.org/D44267 llvm-svn: 327093
* LowerDbgDeclare: ignore dbg.declares for allocas with volatile accessAdrian Prantl2018-03-091-17/+28
| | | | | | | | | | | There is no point in lowering a dbg.declare describing an alloca that has volatile loads or stores as users, since the alloca cannot be elided. Lowering the dbg.declare will result in larger debug info that may also have worse coverage than just describing the alloca. rdar://problem/34496278 llvm-svn: 327092
* Fix header comment on SHA1 code.Eric Christopher2018-03-091-1/+1
| | | | llvm-svn: 327086
* Revert "[DWARF] Fix mixing assembler -g with DWARF .file directives."Paul Robinson2018-03-091-29/+14
| | | | | | | This reverts commit d6d9ac1ab5039ba1fe0f63c36eac2bdd9f0a79c9. aka r327073 llvm-svn: 327083
* Propagate flags to SDValue in SplitVecOp_VECREDUCESameer AbuAsal2018-03-081-2/+2
| | | | | | | | | | | | This patch is a fix for PR36642. While legalizing long vector types, make sure the smaller types get the flags of the wider type. bugzilla link: https://bugs.llvm.org/show_bug.cgi?id=36642 Change-Id: I0c2829639f094c862c10a6b51b342d4c2563e1fa llvm-svn: 327079
* For llvm-objdump and Mach-O files, update the printing of some thread statesKevin Enderby2018-03-081-1/+49
| | | | | | | | | | | from core files. I tested this against the couple of core files that were getting errors about unknown thread flavors and it now produce the same output as the Xcode otool-classic(1) tool. Since the core files are huge I didn’t include them as test cases. rdar://38216356 llvm-svn: 327077
* [DWARF] Fix mixing assembler -g with DWARF .file directives.Paul Robinson2018-03-081-14/+29
| | | | | | | | | | | We were effectively overriding an explicit '.file' directive with info for the assembler source. That shouldn't happen. Fixes PR36636. Differential Revision: https://reviews.llvm.org/D44265 llvm-svn: 327073
* [DebugInfo] Add DW_AT_byte_size to vectorsMatt Davis2018-03-081-1/+32
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds the DW_AT_byte_size dwarf attribute to vectors. This fixes PR21924 LLVM will round a vector up to the next alignable address, which can result in the vector's representation in the object file being larger than what the debugger will calculate via NumberOfElements * ElementSize. In such a case calling sizeof(MyVec) in the source will result in a different value than what a debugger might present. This situation can occur because LLVM permits non-power of two 'vector_size' attributes. Reviewers: echristo, dexonsmith, aprantl Reviewed By: aprantl Subscribers: probinson, aprantl, llvm-commits, JDevlieghere Tags: #debug-info Differential Revision: https://reviews.llvm.org/D44048 llvm-svn: 327072
* [TargetLowering] Remove redundant if condition in SimplifySetcc. NFCCraig Topper2018-03-081-1/+1
| | | | | | We were checking the condition code a second time when we were already in a block with this same condition code check. llvm-svn: 327069
* [DebugInfo] Move RangeListEntries instead of copying.Benjamin Kramer2018-03-081-2/+2
| | | | | | | This is needed for correctness as RangeListEntry is not copy-assignable, which std::vector might rely on. llvm-svn: 327067
* [NFC] Factor out a helper function for checking if a block has a potential ↵Philip Reames2018-03-083-10/+14
| | | | | | early implicit exit. llvm-svn: 327065
* Fix compilation failure with MSVC.Zachary Turner2018-03-081-1/+1
| | | | llvm-svn: 327063
* [asan] Fix a false positive ODR violation due to LTO ConstantMerge pass ↵Kuba Mracek2018-03-081-0/+10
| | | | | | | | | | [llvm part, take 3] This fixes a false positive ODR violation that is reported by ASan when using LTO. In cases, where two constant globals have the same value, LTO will merge them, which breaks ASan's ODR detection. Differential Revision: https://reviews.llvm.org/D43959 llvm-svn: 327061
* Fix signed-unsigned comparison warning.Zachary Turner2018-03-081-1/+1
| | | | llvm-svn: 327060
* [DWARF v5] Support for verbose dumping of .debug_rnglist entriesWolfgang Pieb2018-03-084-28/+98
| | | | | | | | | | | | | | | | Adding verbose dumping to the recent implementation of dumping of v5 range list entries. We're capturing the entries as is as they come in during extraction, including their file offset, so we can dump them in more detail. The offset table entries which are table-relative are shown as is (as in non-verbose mode) and with the actual file offset they map to. Reviewers: dblaikie, aprantl, jdevlieghere, jhenderson Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43366 llvm-svn: 327059
* [ConstantFold] fp_binop undef, undef --> undefSanjay Patel2018-03-081-1/+4
| | | | | | | | | | | | | | | | | These are uncontroversial and independent of a proposed LangRef edits (D44216). I tried to fix tests that would fold away: rL327004 rL327028 rL327030 rL327034 I'm not sure if the Reassociate tests are meaningless yet, but they probably will be as we add more folds, so if anyone has suggestions or wants to fix those, please do. Differential Revision: https://reviews.llvm.org/D44258 llvm-svn: 327058
* [Support] Add WriteThroughMemoryBuffer.Zachary Turner2018-03-083-6/+57
| | | | | | | | | | | This is like MemoryBuffer (read-only) and WritableMemoryBuffer (writable private), but where the underlying file can be modified after writing. This is useful when you want to open a file, make some targeted edits, and then write it back out. Differential Revision: https://reviews.llvm.org/D44230 llvm-svn: 327057
* Revert r327053.Kuba Mracek2018-03-081-7/+0
| | | | llvm-svn: 327055
* [X86][AVX] Pull out variable permute creation from ↵Simon Pilgrim2018-03-081-136/+140
| | | | | | | | LowerBUILD_VECTORAsVariablePermute. NFCI. This will make it easier to handle more complex cases than basic scaling or index masks. llvm-svn: 327054
* [asan] Fix a false positive ODR violation due to LTO ConstantMerge pass ↵Kuba Mracek2018-03-081-0/+7
| | | | | | | | | | [llvm part, take 2] This fixes a false positive ODR violation that is reported by ASan when using LTO. In cases, where two constant globals have the same value, LTO will merge them, which breaks ASan's ODR detection. Differential Revision: https://reviews.llvm.org/D43959 llvm-svn: 327053
* Fix detection of COFF executable files.Zachary Turner2018-03-081-8/+6
| | | | | | | | | | | | One overload of this function would try to identify a file by opening it and using the first 32 bytes to identify the magic of the file. This didn't work properly when more than 32 bytes is actually needed for magic detection to succeed. So now we have this overload read in the entire file. Differential Revision: https://reviews.llvm.org/D44225 llvm-svn: 327050
* [DebugInfo] Add verifier for DICompositeType vectorMatt Davis2018-03-081-0/+8
| | | | | | | | | | | | | | | | | | | Summary: This patch adds verification logic for DICompositeType vectors, ensuring that they only have one element, and that element is of type subrange. This patch complements https://reviews.llvm.org/D44048 Reviewers: aprantl Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D44262 llvm-svn: 327048
* [ThinLTO] Keep available_externally symbols liveVlad Tsyrklevich2018-03-081-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change fixes PR36483. The bug was originally introduced by a change that marked non-prevailing symbols dead. This broke LowerTypeTests handling of available_externally functions, which are non-prevailing. LowerTypeTests uses liveness information to avoid emitting thunks for unused functions. Marking available_externally functions dead is incorrect, the functions are used though the function definitions are not. This change keeps them live, and lets the EliminateAvailableExternally/GlobalDCE passes remove them later instead. I've also enabled EliminateAvailableExternally for all optimization levels, I believe it being disabled for O1 was an oversight. Reviewers: pcc, tejohnson Reviewed By: tejohnson Subscribers: grimar, mehdi_amini, inglorion, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D43690 llvm-svn: 327041
* [Hexagon] Ignore indexed loads when handling unaligned loadsKrzysztof Parzyszek2018-03-081-3/+4
| | | | llvm-svn: 327037
* Expose must/may alias info in MemorySSA.Alina Sbirlea2018-03-081-35/+89
| | | | | | | | | | | | | | | | Summary: Building MemorySSA gathers alias information for Defs/Uses. Store and expose this information when optimizing uses (when building MemorySSA), and when optimizing defs or updating uses (getClobberingMemoryAccess). Current patch does not propagate alias information through MemoryPhis. Reviewers: gbiv, dberlin Subscribers: Prazek, sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38569 llvm-svn: 327035
* Revert r327029Kuba Mracek2018-03-081-6/+0
| | | | llvm-svn: 327033
* [asan] Fix a false positive ODR violation due to LTO ConstantMerge pass ↵Kuba Mracek2018-03-081-0/+6
| | | | | | | | | | [llvm part] This fixes a false positive ODR violation that is reported by ASan when using LTO. In cases, where two constant globals have the same value, LTO will merge them, which breaks ASan's ODR detection. Differential Revision: https://reviews.llvm.org/D43959 llvm-svn: 327029
* [Power9] Add more missing instructions to the Power 9 schedulerStefan Pintilie2018-03-082-40/+276
| | | | | | With this patch we should be able to mark the Power 9 model as complete. llvm-svn: 327021
* AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfoMatt Arsenault2018-03-084-5/+9
| | | | | | These are the parameters x86 already uses. llvm-svn: 327020
* DWARFVerifier: Basic verification of .debug_namesPavel Labath2018-03-081-0/+87
| | | | | | | | | | | | | | | | | Summary: This patch adds basic .debug_names verification capabilities to the DWARF verifier. Right now, it checks that the headers and abbreviation tables of the individual name indexes can be parsed correctly, it verifies the buckets table and the cross-checks the CU lists for consistency. I intend to add further checks in follow-up patches. Reviewers: JDevlieghere, aprantl, probinson, dblaikie Subscribers: vleschuk, echristo, clayborg, llvm-commits Differential Revision: https://reviews.llvm.org/D44211 llvm-svn: 327011
* [DWARF] Don't attempt to parse line tables at invalid offsetsJames Henderson2018-03-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Whilst working on improvements to the error handling of the debug line parsing code, I noticed that if an invalid offset were to be specified in a call to getOrParseLineTable(), an entry in the LineTableMap would still be created, even if the offset was not within the section range. The immediate parsing attempt afterwards would fail (it would end up getting a version of 0), and thereafter, any subsequent calls to getOrParseLineTable or getLineTable would return the default- constructed, invalid line table. In reality, we shouldn't even attempt to parse this table, and we should always return a nullptr from these two functions for this situation. I have tested this via a unit test, which required some new framework for unit testing debug line. My plan is to add quite a few more unit tests for the new error reporting mechanism that will follow shortly, hence the reason why the supporting code for the tests are written the way they are - I intend to extend the DwarfGenerator class to support generating debug line. At that point, I'll make sure that there are a few positive test cases for this and the parsing code too. Differential Revision: https://reviews.llvm.org/D44200 Reviewers: JDevlieghere, aprantl llvm-svn: 326995
* [X86] Change X86::PMULDQ/PMULUDQ opcodes to take vXi64 type as input instead ↵Craig Topper2018-03-086-83/+53
| | | | | | | | | | | | of vXi32. This instruction can be thought of as reading either the even elements of a vXi32 input or the lower half of each element of a vXi64 input. We currently use the vXi32 interpretation, but vXi64 matches better with its broadcast behavior in EVEX. I'm looking at moving MULDQ/MULUDQ creation to a DAG combine so we can do it when AVX512DQ is enabled without having to go through Custom lowering. But in some of the test cases we failed to use a broadcast load due to the size difference. This should help with that. I'm also wondering if we can model these instructions in native IR and remove the intrinsics and I think using a vXi64 type will work better with that. llvm-svn: 326991
* [WebAssembly] Add except_ref as a first-class typeHeejin Ahn2018-03-0811-14/+89
| | | | | | | | | | | | Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]]. Reviewers: dschuff Subscribers: jfb, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D43706 llvm-svn: 326985
* Support resetting STATISTIC() values using llvm::ResetStatistics()Daniel Sanders2018-03-081-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Most of the time, compiler statistics can be obtained using a process that performs a single compilation and terminates such as llc. However, this isn't always the case. JITs for example, perform multiple compilations over their lifetime and STATISTIC() will record cumulative values across all of them. Provide tools like this with the facilities needed to measure individual compilations by allowing them to reset the STATISTIC() values back to zero using llvm::ResetStatistics(). It's still the tools responsibility to ensure that they perform compilations in such a way that the results are meaningful to their intended use. Reviewers: qcolombet, rtereshin, bogner, aditya_nandakumar Reviewed By: bogner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44181 llvm-svn: 326981
* Revert "[LTO] Support filtering by hotness threshold"Bob Haarman2018-03-084-19/+7
| | | | | | | | This reverts commit 1f3bd185c53beb6aa68446974b7e80837abd6ef0 (r326107) because it fails ThinLTO/X86/diagnostic-handler-remarks-with-hotness.ll. llvm-svn: 326975
* Reland "[DebugInfo] Support DWARF expressions in eh_frame"Rafael Auler2018-03-085-369/+263
| | | | | | | | | | Summary: Original change was D43313 (r326932) and reverted by r326953 because it broke an LLD test and a windows build. The LLD test was already fixed in lld commit r326944 (thanks maskray). This is the original change with the windows build fixed. llvm-svn: 326970
* [AArch64] Fix UB about shift amount exceeds data bit-widthWeiming Zhao2018-03-081-1/+1
| | | | | | | | | | | | | | | | Summary: Fixes an UB caught by sanitizer. The shift amount might be larger than 32 so the operand should be 1ULL. In this patch, we replace the original expression with existing API with uint64_t type. Reviewers: eli.friedman, rengolin Reviewed By: rengolin Subscribers: rengolin, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44234 llvm-svn: 326969
* [X86] Fix some isel patterns that used aligned vector load instructions with ↵Craig Topper2018-03-081-76/+76
| | | | | | | | | | unaligned predicates. These patterns weren't checking the alignment of the load, but were using the aligned instructions. This will cause a GP fault if the data isn't aligned. I believe these were introduced in r312450. llvm-svn: 326967
* Delete code that is probably dead since r249303.Rafael Espindola2018-03-081-40/+5
| | | | | | | With r249303 the expression evaluation should expand variables that are not in sections (and so don't have an atom). llvm-svn: 326966
* Fix build broken by r326959Eugene Zemtsov2018-03-081-1/+1
| | | | | | Adding Demangle to link time dependencies of Symbolize llvm-svn: 326964
* [X86][SSE] LowerBUILD_VECTORAsVariablePermute - reorder permute types. NFCI.Simon Pilgrim2018-03-071-15/+15
| | | | | | | | Reorder into 128/256/512 bit vector size groupings. NFCI commit before some new features. llvm-svn: 326963
* Use itaniumDemangle in llvm-symbolizerEugene Zemtsov2018-03-071-9/+4
| | | | | | | | | Currently on Windows (_MSC_VER) LLVMSymbolizer supports only Microsoft mangling. This fix just explicitly uses itaniumDemangle when mangled name starts with _Z. Differential Revision: https://reviews.llvm.org/D44192 llvm-svn: 326959
* [AArch64] Adjust the cost of integer vector divisionEvandro Menezes2018-03-071-22/+38
| | | | | | | | | | Since there is no instruction for integer vector division, factor in the cost of singling out each element to be used with the scalar division instruction. Differential revision: https://reviews.llvm.org/D43974 llvm-svn: 326955
* Revert r326932: [DebugInfo] Support DWARF expressions in eh_frameRui Ueyama2018-03-075-263/+369
| | | | | | This reverts commit rr326932 because it broke lld/test/ELF/eh-frame-hdr-augmentation.s. llvm-svn: 326953
* [AArch64] add missing pattern for insert_subvector undefSebastian Pop2018-03-071-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | The attached testcase started failing after the patch to define isExtractSubvectorCheap with the following pattern mismatch: ISEL: Starting pattern match Initial Opcode index to 85068 Match failed at index 85076 LLVM ERROR: Cannot select: t47: v8i16 = insert_subvector undef:v8i16, t43, Constant:i64<0> The code generated from llvm/lib/Target/AArch64/AArch64InstrInfo.td def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)), (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; is in ninja/lib/Target/AArch64/AArch64GenDAGISel.inc At the location of the error it is: /* 85076*/ OPC_CheckChild2Type, MVT::i32, And it failed to match the type of operand 2. Adding another def-pat for i64 fixes the failed def-pat error: def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i64 0)), (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; llvm-svn: 326949
* [X86] Remove unused function argument. NFCCraig Topper2018-03-071-2/+1
| | | | llvm-svn: 326939
* [DebugInfo] Support DWARF expressions in eh_frameRafael Auler2018-03-075-369/+263
| | | | | | | | | | | | | | | | | | This patch enhances DWARFDebugFrame with the capability of parsing and printing DWARF expressions in CFI instructions. It also makes FDEs and CIEs accessible to lib users, so they can process them in client tools that rely on LLVM. To make it self-contained with a test case, it teaches llvm-readobj to be able to dump EH frames and checks they are correct in a unit test. The llvm-readobj code is Maksim Panchenko's work (maksfb). Reviewers: JDevlieghere, espindola Reviewed By: JDevlieghere Differential Revision: https://reviews.llvm.org/D43313 llvm-svn: 326932
* Update a few switch statements to handle file_magic::pdb.Zachary Turner2018-03-073-0/+5
| | | | | | This fixes a couple of warnings. llvm-svn: 326927
* [Pipeliner] Fixed node order issue related to zero latency edgesRoorda, Jan-Willem2018-03-071-22/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A desired property of the node order in Swing Modulo Scheduling is that for nodes outside circuits the following holds: none of them is scheduled after both a successor and a predecessor. We call node orders that meet this property valid. Although invalid node orders do not lead to the generation of incorrect code, they can cause the pipeliner not being able to find a pipelined schedule for arbitrary II. The reason is that after scheduling the successor and the predecessor of a node, no room may be left to schedule the node itself. For data flow graphs with 0-latency edges, the node ordering algorithm of Swing Modulo Scheduling can generate such undesired invalid node orders. This patch fixes that. In the remainder of this commit message, I will give an example demonstrating the issue, explain the fix, and explain how the the fix is tested. Consider, as an example, the following data flow graph with all edge latencies 0 and all edges pointing downward. ``` n0 / \ n1 n3 \ / n2 | n4 ``` Consider the implemented node order algorithm in top-down mode. In that mode, the algorithm orders the nodes based on greatest Height and in case of equal Height on lowest Movability. Finally, in case of equal Height and Movability, given two nodes with an edge between them, the algorithm prefers the source-node. In the graph, for every node, the Height and Movability are equal to 0. As will be explained below, the algorithm can generate the order n0, n1, n2, n3, n4. So, node n3 is scheduled after its predecessor n0 and after its successor n2. The reason that the algorithm can put node n2 in the order before node n3, even though they have an edge between them in which node n3 is the source, is the following: Suppose the algorithm has constructed the partial node order n0, n1. Then, the nodes left to be ordered are nodes n2, n3, and n4. Suppose that the while-loop in the implemented algorithm considers the nodes in the order n4, n3, n2. The algorithm will start with node n4, and look for more preferable nodes. First, node n4 will be compared with node n3. As the nodes have equal Height and Movability and have no edge between them, the algorithm will stick with node n4. Then node n4 is compared with node n2. Again the Height and Movability are equal. But, this time, there is an edge between the two nodes, and the algorithm will prefer the source node n2. As there are no nodes left to compare, the algorithm will add node n2 to the node order, yielding the partial node order n0, n1, n2. In this way node n2 arrives in the node-order before node n3. To solve this, this patch introduces the ZeroLatencyHeight (ZLH) property for nodes. It is defined as the maximum unweighted length of a path from the given node to an arbitrary node in which each edge has latency 0. So, ZLH(n0)=3, ZLH(n1)=ZLH(n3)=2, ZLH(n2)=1, and ZLH(n4)=0 In this patch, the preference for a greater ZeroLatencyHeight is added in the top-down mode of the node ordering algorithm, after the preference for a greater Height, and before the preference for a lower Movability. Therefore, the two allowed node-orders are n0, n1, n3, n2, n4 and n0, n3, n1, n2, n4. Both of them are valid node orders. In the same way, the bottom-up mode of the node ordering algorithm is adapted by introducing the ZeroLatencyDepth property for nodes. The patch is tested by adding extra checks to the following existing lit-tests: test/CodeGen/Hexagon/SUnit-boundary-prob.ll test/CodeGen/Hexagon/frame-offset-overflow.ll test/CodeGen/Hexagon/vect/vect-shuffle.ll Before this patch, the pipeliner failed to pipeline the loops in these tests due to invalid node-orders. After the patch, the pipeliner successfully pipelines all these loops. Reviewers: bcahoon Reviewed By: bcahoon Subscribers: Ayal, mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D43620 llvm-svn: 326925
* Teach identify_file_magic to identify PDB files.Zachary Turner2018-03-071-1/+3
| | | | llvm-svn: 326924
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