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* PTX: Encode registers as unsigned values in the MC asm printer instead of ↵Justin Holewinski2011-12-064-14/+88
| | | | | | using external symbols llvm-svn: 145946
* use space star instead of star spaceSebastian Pop2011-12-061-9/+9
| | | | llvm-svn: 145944
* add missing point at the end of sentencesSebastian Pop2011-12-061-6/+6
| | | | llvm-svn: 145943
* Simplify common predecessor finding.Benjamin Kramer2011-12-061-24/+10
| | | | | | | | | | | | - Walking over pred_begin/pred_end is an expensive operation. - PHINodes contain a value for each predecessor anyway. - While it may look like we used to save a few iterations with the set, be aware that getIncomingValueForBlock does a linear search on the values of the phi node. - Another -5% on ARMDisassembler.cpp (Release build). This was the last entry in the profile that was obviously wasting time. llvm-svn: 145937
* Push StringRefs through the metadata interface.Benjamin Kramer2011-12-063-4/+4
| | | | llvm-svn: 145934
* Add X86ISD::HADD/HSUB to getTargetNodeNameCraig Topper2011-12-061-0/+2
| | | | llvm-svn: 145929
* Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other ↵Craig Topper2011-12-061-62/+63
| | | | | | integer vector loads are promoted to those. llvm-svn: 145927
* Merge floating point and integer UNPCK X86ISD node types.Craig Topper2011-12-064-167/+104
| | | | llvm-svn: 145926
* Clean up some of the shuffle decoding code for UNPCK instructions. Add ↵Craig Topper2011-12-064-84/+157
| | | | | | instruction commenting for AVX/AVX2 forms for integer UNPCKs. llvm-svn: 145924
* ARM mode 'mul' operand ordering tweak.Jim Grosbach2011-12-061-1/+1
| | | | | | Same as r145922, just for ARM mode. llvm-svn: 145923
* Thumb2: MUL two-operand form encoding operand order fix.Jim Grosbach2011-12-061-1/+1
| | | | | | | | | Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we match gas. rdar://10532439 llvm-svn: 145922
* Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do ↵Craig Topper2011-12-061-140/+37
| | | | | | both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. llvm-svn: 145921
* Thumb2 encoding choice correction for PLD.Jim Grosbach2011-12-061-2/+2
| | | | | | | | Using encoding T1 for offset of #0 and encoding T2 for #-0. rdar://10532413 llvm-svn: 145919
* Use branches instead of jumps + variable cleanup. Testcase coming next. ↵Bruno Cardoso Lopes2011-12-063-41/+39
| | | | | | Patch by Jack Carter llvm-svn: 145912
* Explicit symbols for gnu mimicing relocations. Patch by Jack CarterBruno Cardoso Lopes2011-12-062-0/+20
| | | | llvm-svn: 145911
* Add register HWR29 numbering. Patch by Jack CarterBruno Cardoso Lopes2011-12-062-0/+2
| | | | llvm-svn: 145910
* LSR: prune undesirable formulae early.Andrew Trick2011-12-061-46/+85
| | | | | | | | | It's always good to prune early, but formulae that are unsatisfactory in their own right need to be removed before running any other pruning heuristics. We easily avoid generating such formulae, but we need them as an intermediate basis for forming other good formulae. llvm-svn: 145906
* Mix some minor misuse of MachineBasicBlock iterator.Evan Cheng2011-12-061-3/+3
| | | | llvm-svn: 145903
* Removed isWinToJoinCrossClass from the register coalescer.Pete Cooper2011-12-061-66/+0
| | | | | | | | The new register allocator is much more able to split back up ranges too constrained by register classes. Fixes <rdar://problem/10466609> llvm-svn: 145899
* Kill off the LoopSplitter. It's not being used or maintained.Lang Hames2011-12-065-941/+0
| | | | llvm-svn: 145897
* Add a comment.Bill Wendling2011-12-061-0/+3
| | | | llvm-svn: 145896
* Tidy up value checking.Jim Grosbach2011-12-061-1/+2
| | | | llvm-svn: 145895
* MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.NAKAMURA Takumi2011-12-062-0/+2
| | | | llvm-svn: 145894
* Update PBQP's analysis usage to reflect the requirements of the inline spiller.Lang Hames2011-12-061-0/+7
| | | | llvm-svn: 145893
* [arm-fast-isel] Doublewords only require word-alignment.Chad Rosier2011-12-061-3/+4
| | | | | | rdar://10528060 llvm-svn: 145891
* Align ARM constant pool islands via their basic block.Jakob Stoklund Olesen2011-12-062-2/+7
| | | | | | | | | | | Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment is set on the basic block. This is in preparation of supporting ARM constant pool islands with different alignments. llvm-svn: 145890
* Use logarithmic units for basic block alignment.Jakob Stoklund Olesen2011-12-062-3/+3
| | | | | | | | | | | | | | | | | This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly documented as taking log2(bytes) units, but the x86 target would still set a preferred loop alignment of '16'. CodePlacementOpt passed this number on to the basic block, and AsmPrinter interpreted it as bytes. Now both MachineFunction and MachineBasicBlock use logarithmic alignments. Obviously, MachineConstantPool still measures alignments in bytes, so we can emulate the thrill of using as. llvm-svn: 145889
* The compact encoding of the registers are 3-bits each. Make sure we shift theBill Wendling2011-12-061-2/+4
| | | | | | value over that much. llvm-svn: 145888
* Fix ARM handling of tBcc branch relaxation.Jim Grosbach2011-12-061-3/+5
| | | | | | rdar://10069056 llvm-svn: 145885
* Use an existing function.Jakob Stoklund Olesen2011-12-061-10/+1
| | | | llvm-svn: 145883
* Move target-specific logic out of generic MCAssembler.Jim Grosbach2011-12-066-5/+67
| | | | | | | | Whether a fixup needs relaxation for the associated instruction is a target-specific function, as the FIXME indicated. Create a hook for that and use it. llvm-svn: 145881
* Expose a switch for the new gcov format.Nick Lewycky2011-12-061-2/+3
| | | | llvm-svn: 145880
* Probably not a good idea to convert a single vector load into a memcpy. WeChad Rosier2011-12-061-0/+2
| | | | | | | | don't do this now, but add a test case to prevent this from happening in the future. Additional test for rdar://9892684 llvm-svn: 145879
* Tidy up. Hard tabs.Jim Grosbach2011-12-063-3/+3
| | | | llvm-svn: 145878
* Switch MCAssembler to method names starting w/ lower-case.Jim Grosbach2011-12-064-34/+34
| | | | | | per http://llvm.org/docs/CodingStandards.html#ll_naming llvm-svn: 145873
* Simple branch relaxation for Thumb2 Bcc instructions.Jim Grosbach2011-12-051-3/+24
| | | | | | | Not right yet, as the rules for when to relax in the MCAssembler aren't (yet) correct for ARM. This is a step in the proper direction, though. llvm-svn: 145871
* Silence tsan false-positives (tsan can't track things which are only safe due toNick Lewycky2011-12-051-0/+3
| | | | | | | memory fences) in statistics registration, which works the same way that ManagedStatic registration does. llvm-svn: 145869
* Update comment.Chad Rosier2011-12-051-1/+1
| | | | llvm-svn: 145866
* Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerioChad Rosier2011-12-051-1/+1
| | | | | | | | where this would be bad as the backend shouldn't have a problem inlining small memcpys. rdar://10510150 llvm-svn: 145865
* Tweak ADDrr fix. Bad check for explicit .wJim Grosbach2011-12-051-2/+2
| | | | llvm-svn: 145863
* Thumb2 prefer ADD register encoding T2 to T3 when possible.Jim Grosbach2011-12-051-0/+20
| | | | | | rdar://10529664 llvm-svn: 145860
* Add definitions of 64-bit extract and insert instrucions and makeAkira Hatanaka2011-12-052-12/+17
| | | | | | | PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
* Split ExtIns into two base classes and have instructions EXT and INS derive fromAkira Hatanaka2011-12-051-17/+21
| | | | | | them. llvm-svn: 145852
* Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.Jim Grosbach2011-12-051-0/+18
| | | | | | rdar://10529348 llvm-svn: 145851
* Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 andAkira Hatanaka2011-12-051-20/+16
| | | | | | O32 with relocation-model=pic too. llvm-svn: 145850
* ARM assembly parsing for the rest of the VMUL data type aliases.Jim Grosbach2011-12-052-10/+74
| | | | | | Finish up rdar://10522016. llvm-svn: 145846
* Fix previous commit. Oops.Jim Grosbach2011-12-051-3/+3
| | | | llvm-svn: 145844
* Tidy up. No functional change.Jim Grosbach2011-12-051-9/+6
| | | | llvm-svn: 145843
* ARM assmebler parsing for two-operand VMUL instructions.Jim Grosbach2011-12-052-0/+11
| | | | | | | | | Combined destination and first source operand for f32 variant of the VMUL (by scalar) instruction. rdar://10522016 llvm-svn: 145842
* enable PPC register scavenging by default (update tests and remove some FIXMEs)Hal Finkel2011-12-053-17/+13
| | | | llvm-svn: 145819
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