summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* ARM64: fix SELECT_CC lowering in absence of NaNs.Tim Northover2014-05-101-8/+9
| | | | | | | | | | We were swapping the true & false results while testing for FMAX/FMIN, but not putting them back to the original state if the later checks failed. Should fix PR19700. llvm-svn: 208469
* SLPVectorizer: When sorting by domination for CSE don't assert on ↵Benjamin Kramer2014-05-091-1/+2
| | | | | | | | | | | | unreachable code. There is no total ordering if the CFG is disconnected. We don't care if we catch all CSE opportunities in dead code either so just exclude ignore them in the assert. PR19646 llvm-svn: 208461
* Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"Reid Kleckner2014-05-096-42/+1
| | | | | | | | | | | | | | This reverts commit r200561. This calling convention was an attempt to match the MSVC C++ ABI for methods that return structures by value. This solution didn't scale, because it would have required splitting every CC available on Windows into two: one for methods and one for free functions. Now that we can put sret on the second arg (r208453), and Clang does that (r208458), revert this hack. llvm-svn: 208459
* move findArrayDimensions to ScalarEvolutionSebastian Pop2014-05-092-10/+10
| | | | | | | we do not use the information from SCEVAddRecExpr to compute the shape of the array, so a better place for this function is in ScalarEvolution. llvm-svn: 208456
* fix typo in debug messageSebastian Pop2014-05-091-2/+2
| | | | llvm-svn: 208455
* Allow sret on the second parameter as well as the firstReid Kleckner2014-05-095-36/+45
| | | | | | | | | | | | | | | | | | | | | | | | | MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
* Don't crash on redefinitions.Rafael Espindola2014-05-091-5/+7
| | | | | | | | One error we were not deleting the alias or putting it in the Module. The end result is that there was an use left of the aliasee when the module was deleted. llvm-svn: 208447
* Fix broken buildJonathan Roelofs2014-05-091-1/+1
| | | | | | ARM64 backend was missing a required_library entry. llvm-svn: 208437
* Add custom lowering for add/sub with overflow intrinsics to ARMLouis Gerbarg2014-05-092-0/+97
| | | | | | | | | | | | | This patch adds support to ARM for custom lowering of the llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful for handling idiomatic saturating math functions as generated by InstCombineCompare. Test cases included. rdar://14853450 llvm-svn: 208435
* Add ExtractValue instruction to SimplifyCFG's ComputeSpeculationCostLouis Gerbarg2014-05-091-0/+1
| | | | | | | | | | | | | Since ExtractValue is not included in ComputeSpeculationCost CFGs containing ExtractValueInsts cannot be simplified. In particular this interacts with InstCombineCompare's tendency to insert add.with.overflow intrinsics for certain idiomatic math operations, preventing optimization. This patch adds ExtractValue to the ComputeSpeculationCost. Test case included rdar://14853450 llvm-svn: 208434
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
| | | | llvm-svn: 208432
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-092-7/+6
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
| | | | llvm-svn: 208430
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-094-23/+19
| | | | llvm-svn: 208429
* Use auto and clang-format this snippet.Rafael Espindola2014-05-091-3/+5
| | | | llvm-svn: 208421
* Run clang-format in small sections of code to make a patch easier to read.Rafael Espindola2014-05-092-22/+18
| | | | llvm-svn: 208419
* Delete trailing whitespace.Rafael Espindola2014-05-091-98/+98
| | | | llvm-svn: 208416
* Delete trailing white space.Rafael Espindola2014-05-091-4/+4
| | | | llvm-svn: 208415
* [mips] Marked up instructions added in MIPS-IV and tested that IAS for ↵Daniel Sanders2014-05-095-24/+41
| | | | | | | | | | | | | | | | | | | | | -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-095-27/+239
| | | | | | | | | | When using the ARM AAPCS, HFAs (Homogeneous Floating-point Aggregates) must be passed in a block of consecutive floating-point registers, or on the stack. This means that unused floating-point registers cannot be back-filled with part of an HFA, however this can currently happen. This patch, along with the corresponding clang patch (http://reviews.llvm.org/D3083) prevents this. llvm-svn: 208413
* [mips] Remove unused CondMov feature bitDaniel Sanders2014-05-094-15/+7
| | | | | | | | | | | | | | | Summary: No functional change Depends on D3675 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3676 llvm-svn: 208410
* [mips] Marked up instructions added in MIPS-III and tested that IAS for ↵Daniel Sanders2014-05-096-61/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
* Fix 80 col violation.Andrea Di Biagio2014-05-091-1/+2
| | | | | | No functional change intended. llvm-svn: 208405
* [asan] Stop leaking X86Operands.Benjamin Kramer2014-05-091-4/+4
| | | | llvm-svn: 208400
* [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6Daniel Sanders2014-05-096-2/+189
| | | | | | | | | | | | | | | | | | Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 llvm-svn: 208399
* [mips] Added missing dsra -> dsrav and sra -> srav aliases.Daniel Sanders2014-05-092-2/+6
| | | | | | | | | | | | Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
* MemoryBuffer: don't force mmap when stat failsAlp Toker2014-05-091-3/+2
| | | | | | | Fix error handling introduced in r127426 that could result in MemoryBuffers not having null termination. llvm-svn: 208396
* MemoryBuffer: remove unusued definitionsAlp Toker2014-05-091-8/+0
| | | | | | These were made redundant back in r186560. llvm-svn: 208395
* ARM: support PIC on Windows on ARMSaleem Abdulrasool2014-05-092-2/+27
| | | | | | | | Handle lowering of global addresses for PIC mode compilation on Windows. Always use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and is a pure Thumb environment. llvm-svn: 208385
* printCustom is only used in PseudoSourceValue, remove it from Value.Nick Lewycky2014-05-091-8/+1
| | | | llvm-svn: 208383
* [RuntimeDyld] Unify the RuntimeDyldMachO resolve.*Relocation method signaturesLang Hames2014-05-092-142/+121
| | | | | | | | | around RelocationEntries, rather than passing the same information via loose arguments. No functional change. llvm-svn: 208375
* Optimize shufflevector that copies an i64/f64 and zeros the rest.Filipe Cabecinhas2014-05-081-12/+12
| | | | | | | | | | | | | | Summary: Also ran clang-format on the function. The code added is the last else if block. Reviewers: nadav, craig.topper, delena Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3518 llvm-svn: 208372
* [TargetInstrInfo] Fix the implementation of commuteInstruction to match theQuentin Colombet2014-05-081-4/+2
| | | | | | | | | | | | | comment of the API. Relaxes the behavior of TargetInstrInfo::commuteInstruction when TargetInstrInfo::findCommutedOpIndices returns false. Previously TargetInstrInfo triggered a fatal error in such situation whereas based on the comment in the API it should just return nullptr. Indeed the only precondition that should be ensured is that the instruction must be commutable. llvm-svn: 208371
* Improve wording to make it sounds more like a change than an analysis.Nick Lewycky2014-05-081-2/+3
| | | | llvm-svn: 208370
* Reapply r207876 (Try simplifying LexicalScopes ownership again) including a ↵David Blaikie2014-05-081-28/+35
| | | | | | | | | | | | | | | | | | | workaround for an MSVC2012 bug regarding forward_as_tuple (r207876 was reverted in r208131 after seeing some consistent buildbot failure for MSVC 2012. The original commits were in r207724-r207726) Takumi was nice enough to dig into this and locate this Microsoft Connect issue: http://connect.microsoft.com/VisualStudio/feedback/details/814899/forward-as-tuple-debug-implementation-error describing a bug in MSVC2012's forward_as_tuple implementation. Since the parameters in this instance are trivial/small, pass them by value (using make_tuple) instead of perfectly-forwarded tuple of rvalue references (involving the broken forward_as_tuple). Hopefully this will satisfy MSVC2012. llvm-svn: 208364
* Correct formatting.Tobias Grosser2014-05-081-4/+4
| | | | | | | | Sorry for the commit spam. My clang-format crashed on me and the vim plugin did not print an error, but instead just left the formatting untouched. llvm-svn: 208358
* Use std::remove_if to remove elements from a vectorTobias Grosser2014-05-081-5/+4
| | | | | Suggested-by: Benjamin Kramer <benny.kra@gmail.com> llvm-svn: 208357
* [InstCombine] Some cleanup in optimization of redundant insertvalue ↵Michael Zolotukhin2014-05-081-4/+3
| | | | | | | | instructions. And one more test added. llvm-svn: 208355
* [Hexagon] Add new InstrItinClass to support timing classes.Jyotsna Verma2014-05-085-138/+216
| | | | | | | This patch doesn't introduce any functionality change. Test cases will be added later when v5 support is added. llvm-svn: 208349
* Use for range loops.Rafael Espindola2014-05-081-13/+9
| | | | llvm-svn: 208348
* Use range loop.Rafael Espindola2014-05-081-25/+21
| | | | llvm-svn: 208346
* R600: Promote f64 vector load/stores to i64 for consistencyMatt Arsenault2014-05-081-0/+6
| | | | llvm-svn: 208344
* Use a range loop.Rafael Espindola2014-05-081-4/+2
| | | | llvm-svn: 208343
* [X86] Add target specific combine rules to fold SSE2/AVX2 packed arithmetic ↵Andrea Di Biagio2014-05-081-0/+55
| | | | | | | | | | | | | | | | | | | | shift intrinsics. This patch teaches the backend how to combine packed SSE2/AVX2 arithmetic shift intrinsics. The rules are: - Always fold a packed arithmetic shift by zero to its first operand; - Convert a packed arithmetic shift intrinsic dag node into a ISD::SRA only if the shift count is known to be smaller than the vector element size. This patch also teaches to function 'getTargetVShiftByConstNode' how fold target specific vector shifts by zero. Added two new tests to verify that the DAGCombiner is able to fold sequences of SSE2/AVX2 packed arithmetic shift calls. llvm-svn: 208342
* [mips] Add PredicateControl to InstAlias'sDaniel Sanders2014-05-084-107/+115
| | | | | | | | | | | | | | | Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 llvm-svn: 208334
* [ARM64] Add diagnostics for expected arithmetic shiftsBradley Smith2014-05-083-14/+32
| | | | llvm-svn: 208330
* [ARM64] Re-work parsing of ADD/SUB shifted immediate operandsBradley Smith2014-05-083-130/+210
| | | | | | | | | | | | The parsing of ADD/SUB shifted immediates needs to be done explicitly so that better diagnostics can be emitted, as a side effect this also removes some of the hacks in the current method of handling this operand type. Additionally remove manual CMP aliasing to ADD/SUB and use InstAlias instead. llvm-svn: 208329
* [ARM64] Ensure immediates in extend operands are in a valid rangeBradley Smith2014-05-082-4/+19
| | | | | | Also emit a more useful diagnostic when they are not. llvm-svn: 208318
* [ARM64] Check for proper immediate in shift/extend operandsBradley Smith2014-05-081-42/+58
| | | | llvm-svn: 208317
* ARM big endian function argument passingChristian Pirker2014-05-081-11/+30
| | | | llvm-svn: 208316
OpenPOWER on IntegriCloud