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* Change getX86SubSuperRegister to take an MVT::SimpleValueType rather than an ↵Craig Topper2012-09-304-11/+12
| | | | | | EVT and add llvm_unreachable to the switches. Helps it compile to dramatically better code. llvm-svn: 164919
* ArgumentPromotion: Remove ancient workaround for a bug in the C backend.Benjamin Kramer2012-09-301-19/+1
| | | | | | Fun fact: The CBE learned how to deal with this situation before it was removed. llvm-svn: 164918
* Ignore apparent buffer overruns on external or weak globals. This is a majorDuncan Sands2012-09-301-7/+11
| | | | | | | source of false positives due to globals being declared in a header with some kind of incomplete (small) type, but the actual definition being bigger. llvm-svn: 164912
* Revert r164910 because it causes failures to several phase2 builds.Nadav Rotem2012-09-301-254/+0
| | | | llvm-svn: 164911
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-301-0/+254
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164910
* Add LLVM support for Swift.Bob Wilson2012-09-2918-63/+1810
| | | | llvm-svn: 164899
* Whitespace.Bob Wilson2012-09-291-1/+1
| | | | llvm-svn: 164898
* Shrink TargetAlignElem a bit, we do a lot of searches on them.Benjamin Kramer2012-09-291-0/+2
| | | | llvm-svn: 164897
* Fix a somewhat surprising miscompile where code relying on an ABIChandler Carruth2012-09-291-3/+13
| | | | | | | | | | | | | | | alignment could lose it due to the alloca type moving down to a much smaller alignment guarantee. Now SROA will actively compute a proper alignment, factoring the target data, any explicit alignment, and the offset within the struct. This will in some cases lower the alignment requirements, but when we lower them below those of the type, we drop the alignment entirely to give freedom to the code generator to align it however is convenient. Thanks to Duncan for the lovely test case that pinned this down. =] llvm-svn: 164891
* Speculatively revert commit 164885 (nadav) in the hope of ressurecting a pile ofDuncan Sands2012-09-291-252/+0
| | | | | | | | | | | | | | | | | | | | buildbots. Original commit message: A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164890
* Tidy up to match coding standards. Remove 'else' after 'return' and moving ↵Craig Topper2012-09-291-27/+24
| | | | | | operators to end of preceding line. No functional change intended. llvm-svn: 164887
* Replace a couple if/elses around similar calls with conditional operators on ↵Craig Topper2012-09-291-17/+6
| | | | | | the varying arguments. No functional change. llvm-svn: 164886
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-291-0/+252
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164885
* Do not delete BBs if their addresses are taken. rdar://12396696Evan Cheng2012-09-281-2/+3
| | | | llvm-svn: 164866
* Don't use bit-wise operations to query for inclusion/exclusion of attributes.Bill Wendling2012-09-281-14/+49
| | | | llvm-svn: 164860
* GlobalDCE should be run at -O2 / -Os to eliminate unused dtor, etc. ↵Evan Cheng2012-09-281-4/+3
| | | | | | rdar://9142819 llvm-svn: 164850
* MIPS DSP: other miscellaneous instructions.Akira Hatanaka2012-09-282-0/+136
| | | | llvm-svn: 164845
* MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka2012-09-282-0/+112
| | | | llvm-svn: 164840
* X86: when replacing SUB with TEST in ISelDAGToDAG, only replace uses of theManman Ren2012-09-281-5/+28
| | | | | | | | second output of SUB with first output of TEST. PR13966 llvm-svn: 164835
* Removing dependency on third party library for Intel JIT event support.Andrew Kaylor2012-09-288-10/+1350
| | | | | | Patch committed on behalf of Kirill Uhanov llvm-svn: 164831
* Replace the use of strncpy() and sprintf() with std::string and LLVM streams.Dmitri Gribenko2012-09-281-4/+7
| | | | | | Patch by Martinez, Javier E. llvm-svn: 164822
* CorrelatedPropagation: BasicBlock::removePredecessor can simplify PHI nodes. ↵Benjamin Kramer2012-09-281-0/+5
| | | | | | | | If the it's the condition of a SwitchInst, reload it. Fixes PR13972. llvm-svn: 164818
* Make backtraces work again with both the configure and cmake build.Benjamin Kramer2012-09-281-1/+1
| | | | llvm-svn: 164817
* GlobalOpt: non-constexpr bitcasts or GEPs can occur even if the global value ↵Benjamin Kramer2012-09-281-1/+3
| | | | | | | | is only stored once. Fixes PR13968. llvm-svn: 164815
* Surprisingly, we missed a trivial case here. Fix that!Nick Lewycky2012-09-281-0/+4
| | | | llvm-svn: 164814
* 1. Add load/store words from the stackReed Kotler2012-09-283-34/+86
| | | | | | | | | 2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and moved other lines for FEXT_RI16 formats to be in the right place in the code. 3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment. 4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem. llvm-svn: 164811
* Remove <def,read-undef> flags from partial redefinitions.Jakob Stoklund Olesen2012-09-271-0/+6
| | | | | | | | | The new coalescer can turn a full virtual register definition into a partial redef by merging another value into an unused vector lane. Make sure to clear the <read-undef> flag on such defs. llvm-svn: 164807
* Enable the new coalescer algorithm by default.Jakob Stoklund Olesen2012-09-271-1/+1
| | | | | | | The new coalescer is better at merging values into unused vector lanes, improving NEON code. llvm-svn: 164794
* Don't dereference begin() on an empty vector.Jakob Stoklund Olesen2012-09-271-1/+1
| | | | | | | | The fix is obvious and the only test case I have is horrible, so I am not including it. The problem shows up when self-hosting clang on i386 with -new-coalescer enabled. llvm-svn: 164793
* MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka2012-09-272-0/+162
| | | | llvm-svn: 164787
* MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+151
| | | | llvm-svn: 164786
* Fix a integer overflow in SimplifyCFG's look up table formation logic.Benjamin Kramer2012-09-271-0/+4
| | | | | | | | If the width is very large it gets truncated from uint64_t to uint32_t when passed to TD->fitsInLegalInteger. The truncated value can fit in a register. This manifested in massive memory usage or crashes (PR13946). llvm-svn: 164784
* Avoid dereferencing a NULL pointer.Jakob Stoklund Olesen2012-09-271-1/+1
| | | | | | Fixes PR13943. llvm-svn: 164778
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-2742-128/+128
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-2742-128/+128
| | | | llvm-svn: 164767
* Prefer shuffles to selects. Backends love shuffles!Nick Lewycky2012-09-271-1/+19
| | | | llvm-svn: 164763
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-275-2/+123
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).Akira Hatanaka2012-09-272-0/+26
| | | | llvm-svn: 164756
* MIPS DSP: CMPU.EQ.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+224
| | | | llvm-svn: 164755
* MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+195
| | | | llvm-svn: 164754
* MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka2012-09-274-0/+103
| | | | | | Field instruction. llvm-svn: 164751
* MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka2012-09-273-0/+444
| | | | llvm-svn: 164750
* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-274-0/+224
| | | | llvm-svn: 164749
* MIPS DSP: add functions which decode DSP and accumulator registers.Akira Hatanaka2012-09-271-0/+29
| | | | llvm-svn: 164748
* MIPS DSP: add code necessary for pseudo instruction lowering.Akira Hatanaka2012-09-275-2/+22
| | | | llvm-svn: 164747
* MIPS DSP: add bitcast patterns between vectors and int.Akira Hatanaka2012-09-271-0/+10
| | | | | | No test cases. These patterns will get tested along with dsp intrinsics. llvm-svn: 164746
* MIPS DSP: add vector load/store patterns.Akira Hatanaka2012-09-272-0/+18
| | | | llvm-svn: 164744
* Fix of hang during Intel JIT profilingAndrew Kaylor2012-09-261-11/+9
| | | | | | Committed on behalf of Kirill Uhanov llvm-svn: 164736
* Disable the new SROA pass to get the tree back in working order. We don't yetNick Lewycky2012-09-261-1/+1
| | | | | | have testcases for the current problems. llvm-svn: 164731
* Add IRBuilder code for adding !tbaa.struct metadata tags to llvm.memcpy calls.Dan Gohman2012-09-261-1/+5
| | | | llvm-svn: 164728
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