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* Add operator< for FoldingSetNodeID.Ted Kremenek2012-09-081-0/+18
| | | | llvm-svn: 163454
* Remove an incorrect assert during branch weight propagation.Andrew Trick2012-09-081-1/+0
| | | | | | Patch and test case by Alastair Murray! llvm-svn: 163437
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-077-12/+20
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. llvm-svn: 163420
* Fix indent.Chad Rosier2012-09-071-2/+2
| | | | llvm-svn: 163416
* Contrary to what the documentation says, .lcomm alignment on COFF is in ↵Benjamin Kramer2012-09-071-1/+1
| | | | | | bytes, not power of 2. llvm-svn: 163405
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-072-49/+48
| | | | llvm-svn: 163401
* Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen2012-09-071-6/+3
| | | | | | | The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. llvm-svn: 163396
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-0710-21/+28
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-071-5/+6
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. llvm-svn: 163390
* MipsAsmParser: Fix a couple of string use-after-frees and misuses of classof.Benjamin Kramer2012-09-071-8/+8
| | | | llvm-svn: 163383
* SimplifyCFG: ValidLookupTableConstant should be staticHans Wennborg2012-09-071-1/+1
| | | | llvm-svn: 163378
* Stop emitting lifetime region info when stack coloring is not enabled in O0Michael Liao2012-09-071-0/+6
| | | | | | - this should fix PR13780 llvm-svn: 163370
* The Mips standalone assembler aliased instruction support.Jack Carter2012-09-071-0/+20
| | | | | | | | | | | | | | The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
* The Mips standalone assembler intial directive support.Jack Carter2012-09-071-0/+43
| | | | | | | | | | Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic llvm-svn: 163364
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-072-7/+220
| | | | | | | Test cases included Contributer: Vladimir Medic llvm-svn: 163363
* Re-work bit/bits value resolving in tblgenMichael Liao2012-09-062-138/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. llvm-svn: 163360
* Remove unused variable introduced by r163346.David Blaikie2012-09-061-2/+0
| | | | llvm-svn: 163359
* The Mips standalone assembler memory instruction support.Jack Carter2012-09-061-7/+211
| | | | | | | | | This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw Test case included Contributer: Vladimir Medic llvm-svn: 163346
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-0622-0/+60
| | | | | | No functional change. llvm-svn: 163344
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-0620-0/+54
| | | | | | No functional change. llvm-svn: 163339
* Allow overlaps between virtreg and physreg live ranges.Jakob Stoklund Olesen2012-09-063-1/+53
| | | | | | | | | | | | | | | | | The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. llvm-svn: 163336
* Handle overlapping regunit intervals in LiveIntervals::addKillFlags().Jakob Stoklund Olesen2012-09-062-3/+45
| | | | | | | | | | | | | | | | | | We will soon allow virtual register live ranges to overlap regunit live ranges when the physreg is defined as a copy of the virtreg: %EAX = COPY %vreg5 FOO %vreg5 BAR %EAX<kill> There is no real interference since %vreg5 and %EAX have the same value where they overlap. This patch prevents addKillFlags from adding virtreg kill flags to FOO where the assigned physreg is overlapping the virtual register live range. llvm-svn: 163335
* Clear kill flags while computing live ranges.Jakob Stoklund Olesen2012-09-061-1/+5
| | | | | | | | | Kill flags are difficult to maintain, and liveness queries are better handled by live intervals. Kill flags are reinserted after register allocation by addKillFlags(). llvm-svn: 163334
* Dont cast away const needlessly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-063-3/+4
| | | | llvm-svn: 163324
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-061-8/+38
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* BasicAA: Recognize cyclic NoAlias phisArnold Schwaighofer2012-09-061-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhances basic alias analysis to recognize phis whose first incoming values are NoAlias and whose other incoming values are just the phi node itself through some amount of recursion. Example: With this change basicaa reports that ptr_phi and ptr_phi2 do not alias each other. bb: ptr = ptr2 + 1 loop: ptr_phi = phi [bb, ptr], [loop, ptr_plus_one] ptr2_phi = phi [bb, ptr2], [loop, ptr2_plus_one] ... ptr_plus_one = gep ptr_phi, 1 ptr2_plus_one = gep ptr2_phi, 1 This enables the elimination of one load in code like the following: extern int foo; int test_noalias(int *ptr, int num, int* coeff) { int *ptr2 = ptr; int result = (*ptr++) * (*coeff--); while (num--) { *ptr2++ = *ptr; result += (*coeff--) * (*ptr++); } *ptr = foo; return result; } Part 2/2 of fix for PR13564. llvm-svn: 163319
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-2/+2
| | | | | | Patch by Chris Lidbury. llvm-svn: 163318
* BasicAA: GEPs of NoAlias'ing base ptr with equivalent indices are NoAliasArnold Schwaighofer2012-09-061-9/+65
| | | | | | | | | | | | If we can show that the base pointers of two GEPs don't alias each other using precise analysis and the indices and base offset are equal then the two GEPs also don't alias each other. This is primarily needed for the follow up patch that analyses NoAlias'ing PHI nodes. Part 1/2 of fix for PR13564. llvm-svn: 163317
* Disable stack coloring by default in order to resolve the i386 failures.Nadav Rotem2012-09-061-1/+1
| | | | llvm-svn: 163316
* AVX2 optimization.Elena Demikhovsky2012-09-061-0/+40
| | | | | | Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible. llvm-svn: 163312
* Fix a few old-GCC warnings. No functional change.Nadav Rotem2012-09-062-2/+2
| | | | llvm-svn: 163309
* Fix self-host; ensure signedness is consistent.James Molloy2012-09-061-2/+2
| | | | llvm-svn: 163306
* Fix switch_to_lookup_table.ll test from r163302.Hans Wennborg2012-09-061-5/+6
| | | | | | | | The lookup tables did not get built in a deterministic order. This makes them get built in the order that the corresponding phi nodes were found. llvm-svn: 163305
* Improve codegen for BUILD_VECTORs on ARM.James Molloy2012-09-061-10/+56
| | | | | | If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base. llvm-svn: 163304
* Build lookup tables for switches (PR884)Hans Wennborg2012-09-061-0/+286
| | | | | | | | | | | | | | | | | | | | | | This adds a transformation to SimplifyCFG that attemps to turn switch instructions into loads from lookup tables. It works on switches that are only used to initialize one or more phi nodes in a common successor basic block, for example: int f(int x) { switch (x) { case 0: return 5; case 1: return 4; case 2: return -2; case 5: return 7; case 6: return 9; default: return 42; } This speeds up the code by removing the hard-to-predict jump, and reduces code size by removing the code for the jump targets. llvm-svn: 163302
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-0612-8/+712
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate ↵James Molloy2012-09-062-17/+66
| | | | | | to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. llvm-svn: 163298
* Remove duplicated helper functionMichael Liao2012-09-061-17/+1
| | | | llvm-svn: 163295
* Use iPTR instead of i32 for extract_subvector/insert_subvector index in ↵Craig Topper2012-09-062-78/+78
| | | | | | lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. llvm-svn: 163293
* Add patterns for converting stores of subvector_extracts of lower 128-bits ↵Craig Topper2012-09-061-0/+40
| | | | | | of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. llvm-svn: 163292
* Whitespace.NAKAMURA Takumi2012-09-061-2/+2
| | | | llvm-svn: 163289
* Unix/Signals.inc: Fix a typo. Thanks to Dani Berg!NAKAMURA Takumi2012-09-061-1/+1
| | | | llvm-svn: 163288
* There are some Mips instructions that are lowered by the Jack Carter2012-09-066-95/+124
| | | | | | | | | | | | | | | | assembler such as shifts greater than 32. In the case of direct object, the code gen needs to do this lowering since the assembler is not involved. With the advent of the llvm-mc assembler, it also needs to do the same lowering. This patch makes that specific lowering code accessible to both the direct object output and the assembler. This patch does not affect generated output. llvm-svn: 163287
* Update function names to conform to guidelines.Jim Grosbach2012-09-061-26/+26
| | | | | | No functional change. llvm-svn: 163279
* Mips specific llvm assembler support for branch and jump instructions.Jack Carter2012-09-061-2/+9
| | | | | | | Test case included. Contributer: Vladimir Medic llvm-svn: 163277
* Remove predicated pseudo-instructions.Jakob Stoklund Olesen2012-09-052-100/+0
| | | | | | | These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. llvm-svn: 163275
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-051-56/+31
| | | | | | | | | | | | | | | | | | | | Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
* [ms-inline asm] Use the asm dialect from the MI to set the parser dialect.Chad Rosier2012-09-051-2/+4
| | | | llvm-svn: 163273
* JumpThreading: when default destination is the destination of some cases in aManman Ren2012-09-051-3/+6
| | | | | | | | | switch, make sure we include the value for the cases when calculating edge value from switch to the default destination. rdar://12241132 llvm-svn: 163270
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