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* Add missing break statements. Align UNWIND_INFO and RUNTIME_FUNCTION structsCharles Davis2011-05-271-0/+6
| | | | | | | | to 4 bytes. I'm surprised no one caught the missing break statements. llvm-svn: 132176
* My attempt at fixing the leak reported by the valgrind buildbots. Valgrind willCharles Davis2011-05-271-2/+4
| | | | | | | | still report leaks, but they're spurious now. Valgrind cannot peer into std::vector objects--or any dynamic array, for that matter--because it doesn't know how big the array is. llvm-svn: 132174
* Fix inverted conditional in SaveReg and SaveXMM. Err when the frame pointer isCharles Davis2011-05-271-3/+7
| | | | | | | already defined, and err when the PushMachFrame operation isn't the first operation (if specified at all). llvm-svn: 132173
* One more debug line number miss in instcombine (although the code in ↵Eli Friedman2011-05-271-5/+1
| | | | | | question isn't actually in instcombine). llvm-svn: 132170
* Final step of instcombine debuginfo; switch a couple more places over to ↵Eli Friedman2011-05-275-16/+34
| | | | | | InsertNewInstWith, and use setDebugLoc for the cases which can't be easily handled by the automated mechanisms. llvm-svn: 132167
* Fix warning about || and && without explicit grouping.Chandler Carruth2011-05-261-2/+2
| | | | | | | | This looks like it flagged an actual bug. Devang, please review. I added the parentheses that change behavior, but make the behavior more closely match commit log's intent. llvm-svn: 132165
* Do not insert anything after terminator.Devang Patel2011-05-261-1/+2
| | | | llvm-svn: 132164
* Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. Chad Rosier2011-05-264-25/+51
| | | | | | | crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
* Do not move DBG_VALUE in middle of PHI nodes.Devang Patel2011-05-261-1/+4
| | | | llvm-svn: 132161
* If llvm.dbg.value and the value instruction it refers to are far apart then ↵Devang Patel2011-05-261-1/+13
| | | | | | iSel may not be able to find corresponding Node for llvm.dbg.value during DAG construction. Make iSel's life easier by removing this distance between llvm.dbg.value and its value instruction. llvm-svn: 132151
* Add comment.Devang Patel2011-05-261-0/+3
| | | | llvm-svn: 132149
* During branch folding avoid inserting redundant DBG_VALUE machine instructions.Devang Patel2011-05-261-0/+13
| | | | llvm-svn: 132148
* Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check ifAkira Hatanaka2011-05-263-10/+2
| | | | | | a function has any function calls. llvm-svn: 132140
* Fix some dwarf register numbers.Rafael Espindola2011-05-263-3/+3
| | | | llvm-svn: 132136
* Fix LTO builds with xcode 4.Rafael Espindola2011-05-261-1/+11
| | | | llvm-svn: 132132
* Add support for C++ exception handling.Akira Hatanaka2011-05-266-13/+68
| | | | llvm-svn: 132131
* Reorganize these slightly according to operand type.Eric Christopher2011-05-261-2/+2
| | | | llvm-svn: 132128
* Set HasSetDirective to true.Akira Hatanaka2011-05-261-1/+0
| | | | llvm-svn: 132127
* Revert r132111. I built Release (without Asserts), so I didn't know about theCharles Davis2011-05-261-2/+0
| | | | | | assert that prevented setting alignment on section creation. llvm-svn: 132113
* Align Win64 EH Table sections to 4 bytes.Charles Davis2011-05-261-0/+2
| | | | llvm-svn: 132111
* Reverting 132105: it broke some LLVM-GCC DejaGNU tests.Stuart Hastings2011-05-263-81/+15
| | | | llvm-svn: 132108
* Mark tBX as an indirect branch rather than a return.Cameron Zwarich2011-05-262-9/+9
| | | | llvm-svn: 132107
* Test .seh_startchained and .seh_endchained parsing.Charles Davis2011-05-261-13/+13
| | | | | | | | | | | Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with chained unwind areas exposed by the test that were related to this. The ChainedParent field had the wrong address, because when the chained unwind info was added, the addresses shifted around. Now we store the pointers to the structures, which are now allocated from the MC heap. llvm-svn: 132106
* Correctly handle a one-word struct passed byval on x86_64.Stuart Hastings2011-05-263-15/+81
| | | | | | rdar://problem/6920088 llvm-svn: 132105
* indvars: incremental fixes for -disable-iv-rewrite and testcases.Andrew Trick2011-05-261-21/+72
| | | | | | | | Use a proper worklist for use-def traversal without holding onto an iterator. Now that we process all IV uses, we need complete logic for resusing existing derived IV defs. See HoistStep. llvm-svn: 132103
* Add a RAGreedy::canEvict function.Jakob Stoklund Olesen2011-05-251-4/+62
| | | | | | | | | | | | This doesn't change functionality (much), but it allows for a more fine-grained eviction policy. The current policy only compares spill weights, and that is not always the best thing to do. Spill weights are designed to serve linear scan, and they don't consider live range splitting. Add a mechanism so canEvict() can request that a live range be evicted and split/spilled. This is to avoid infinite eviction loops. llvm-svn: 132101
* Rewrite fast-isel integer cast handling to handle more cases, and to be ↵Eli Friedman2011-05-253-52/+126
| | | | | | | | | | simpler and more consistent. The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts). rdar://9437928 . llvm-svn: 132099
* Define WeakRefDirective.Akira Hatanaka2011-05-251-0/+1
| | | | llvm-svn: 132098
* PR9998: ashr exact %x, 31 is not equivalent to sdiv exact %x, -2147483648.Eli Friedman2011-05-251-4/+4
| | | | llvm-svn: 132097
* Remove unused statistical counter.Devang Patel2011-05-251-57/+0
| | | | llvm-svn: 132087
* Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.Cameron Zwarich2011-05-252-10/+24
| | | | llvm-svn: 132086
* Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues withCharles Davis2011-05-252-2/+15
| | | | | | | | | | them. I had to add a special SwitchSectionNoChange method to MCStreamer just for .seh_handlerdata. If this isn't OK, please let me know, and I'll find some other way to fix .seh_handlerdata streaming. llvm-svn: 132084
* Clean up comment a bit.Eric Christopher2011-05-251-2/+2
| | | | llvm-svn: 132083
* Implement the 'm' modifier. Note that it only works for memory operands.Eric Christopher2011-05-251-4/+14
| | | | | | Part of rdar://9119939 llvm-svn: 132081
* Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have alreadyAkira Hatanaka2011-05-252-37/+0
| | | | | | been defined in MipsInstrFPU.td. llvm-svn: 132076
* Custom-lower FCOPYSIGN nodes.Akira Hatanaka2011-05-252-2/+58
| | | | llvm-svn: 132074
* Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for ↵Eli Friedman2011-05-251-0/+4
| | | | | | i8 and i16 values. llvm-svn: 132073
* Simplify r132022 based on Cameron's feedback.Evan Cheng2011-05-251-12/+5
| | | | llvm-svn: 132071
* Update MaxCallFrameSize regardless of the relocation model selected.Akira Hatanaka2011-05-251-11/+11
| | | | llvm-svn: 132070
* Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() shouldAkira Hatanaka2011-05-253-7/+7
| | | | | | return 0 if there are no function calls made. llvm-svn: 132065
* Coding style fixes. Added comments.Akira Hatanaka2011-05-252-23/+16
| | | | llvm-svn: 132063
* Remove unused OpcodeMask enumerator.Francois Pichet2011-05-251-1/+0
| | | | llvm-svn: 132062
* Fix MSVC warning: "is out of range for enum constant" Francois Pichet2011-05-251-1/+1
| | | | | | | MSVC doesn't support 64 bit enum. OpcodeMask is not used anywhere in the code base. llvm-svn: 132057
* Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix theCharles Davis2011-05-251-6/+17
| | | | | | buggy methods that parse these directives. llvm-svn: 132045
* Restore an accidentally removed comment.Cameron Zwarich2011-05-251-0/+1
| | | | llvm-svn: 132044
* Move some code to a more logical place.Cameron Zwarich2011-05-251-8/+8
| | | | llvm-svn: 132043
* Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. ThisCameron Zwarich2011-05-251-1/+1
| | | | | | fixes <rdar://problem/9495913> llvm-svn: 132042
* Change the order of tBX's operands so that the predicate operands come after theCameron Zwarich2011-05-252-2/+11
| | | | | | | | | target register, matching BX. I filed this bug because I was confused at first: PR10007 - ARM branch instructions have inconsistent predicate operand placement <http://llvm.org/bugs/show_bug.cgi?id=10007> llvm-svn: 132041
* Rename tBX_Rm to tBX.Cameron Zwarich2011-05-252-5/+4
| | | | llvm-svn: 132040
* Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to betterCameron Zwarich2011-05-252-3/+3
| | | | | | reflect their actual meaning and match the ARM instructions. llvm-svn: 132039
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