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* Refactor operation equivalence checking in BBVectorize by extending ↵Hal Finkel2012-06-282-28/+18
| | | | | | | | | | | Instruction::isSameOperationAs. Maintaining this kind of checking in different places is dangerous, extending Instruction::isSameOperationAs consolidates this logic into one place. Here I've added an optional flags parameter and two flags that are important for vectorization: CompareIgnoringAlignment and CompareUsingScalarTypes. llvm-svn: 159329
* Only print out the tag if it's there.Bill Wendling2012-06-281-1/+2
| | | | llvm-svn: 159328
* Don't output an empty string.Bill Wendling2012-06-281-2/+3
| | | | llvm-svn: 159327
* The Mips specific inline asm operand modifier 'z' has theJack Carter2012-06-281-1/+13
| | | | | | | | following description in the gnu sources: Print $0 if operand is zero otherwise print the op normally. llvm-svn: 159324
* make LVI::getEdgeValue() always intersect the constraints of the edge with ↵Nuno Lopes2012-06-281-36/+53
| | | | | | the range of the block. Previously it was only performing the intersection for a few cases, thus losing precision llvm-svn: 159320
* fix a off-by-one bug in intersectWith(), and add a bunch of testsNuno Lopes2012-06-281-1/+1
| | | | llvm-svn: 159319
* Use the interface through DIDescriptor to get the tag/version for a debug infoBill Wendling2012-06-281-9/+11
| | | | | | MDNode. llvm-svn: 159317
* Fix cmake failure from moving files around.Bill Wendling2012-06-282-1/+1
| | | | llvm-svn: 159314
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-2838-103/+101
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* This allows hello world to be compiled for Mips 64 direct object.Jack Carter2012-06-271-0/+1
| | | | | | | | | | | It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack llvm-svn: 159302
* This allows hello world to be compiled for Mips 64 direct object.Jack Carter2012-06-274-3/+54
| | | | | | | | | | | It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack llvm-svn: 159301
* Whitespace.Chad Rosier2012-06-271-34/+34
| | | | llvm-svn: 159300
* The ELF relocation record format is different for N64 Jack Carter2012-06-273-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | which many Mips 64 ABIs use than for O64 which many if not all other target ABIs use. Most architectures have the following 64 bit relocation record format: typedef struct { Elf64_Addr r_offset; /* Address of reference */ Elf64_Xword r_info; /* Symbol index and type of relocation */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset; Elf64_Xword r_info; Elf64_Sxword r_addend; } Elf64_Rela; Whereas N64 has the following format: typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ Elf64_Sxword r_addend; } Elf64_Rela; The structure is the same size, but the r_info data element is now 5 separate elements. Besides the content aspects, endian byte reordering will be different for the area with each element being endianized separately. I treat this as generic and continue to pass r_type as an integer masking and unmasking the byte sized N64 values for N64 mode. I've implemented this and it causes no affect on other current targets. This passes make check. Jack llvm-svn: 159299
* Revert r159136 due to PR13124.Matt Beaumont-Gay2012-06-271-11/+0
| | | | | | | | | | | Original commit message: If a constant or a function has linkonce_odr linkage and unnamed_addr, mark it hidden. Being linkonce_odr guarantees that it is available in every dso that needs it. Being a constant/function with unnamed_addr guarantees that the copies don't have to be merged. llvm-svn: 159272
* Some reassociate optimizations create new instructions, which they insert justDuncan Sands2012-06-271-11/+7
| | | | | | | | | | | before the expression root. Any existing operators that are changed to use one of them needs to be moved between it and the expression root, and recursively for the operators using that one. When I rewrote RewriteExprTree I accidentally inverted the logic, resulting in the compacting going down from operators to operands rather than up from operands to the operators using them, oops. Fix this, resolving PR12963. llvm-svn: 159265
* Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton2012-06-271-1/+1
| | | | llvm-svn: 159259
* Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton2012-06-271-1/+2
| | | | | | instruction llvm-svn: 159257
* Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka2012-06-271-1/+1
| | | | llvm-svn: 159243
* Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2012-06-272-3/+10
| | | | llvm-svn: 159240
* Reduce indentation in function. Rearrange some methods. No functionality change.Bill Wendling2012-06-261-223/+222
| | | | llvm-svn: 159239
* Revamp how debugging information is emitted for debug info objects.Bill Wendling2012-06-261-134/+84
| | | | | | | | | It's not necessary for each DI class to have its own copy of `print' and `dump'. Instead, just give DIDescriptor those methods and have it call the appropriate debugging printing routine based on the type of the debug information. llvm-svn: 159237
* Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng2012-06-261-0/+2
| | | | | | possible. Sorry. rdar://11745134 llvm-svn: 159236
* Remove a instcombine transform that (no longer?) makes sense:Evan Cheng2012-06-261-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // C - zext(bool) -> bool ? C - 1 : C if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1)) if (ZI->getSrcTy()->isIntegerTy(1)) return SelectInst::Create(ZI->getOperand(0), SubOne(C), C); This ends up forming sext i1 instructions that codegen to terrible code. e.g. int blah(_Bool x, _Bool y) { return (x - y) + 1; } => movzbl %dil, %eax movzbl %sil, %ecx shll $31, %ecx sarl $31, %ecx leal 1(%rax,%rcx), %eax ret Without the rule, llvm now generates: movzbl %sil, %ecx movzbl %dil, %eax incl %eax subl %ecx, %eax ret It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-). The transformation was done as part of Eli's r75531. He has given the ok to remove it. rdar://11748024 llvm-svn: 159230
* Implement getHostCPUName for ARM/linux. This will be used to implement ↵Benjamin Kramer2012-06-261-0/+55
| | | | | | | | | | -march=native in clang. The cpuid registers are only available in privileged mode so we don't have an OS-independent way of implementing this. ARM doesn't provide a list of processor IDs so the list is somewhat incomplete. llvm-svn: 159228
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-267-4/+132
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Fix ThreadLocalImpl::getInstance for --disable-threads.Argyrios Kyrtzidis2012-06-261-3/+5
| | | | | | PR13114. llvm-svn: 159210
* Allow targets to inject passes before the virtual register rewriter.Jakob Stoklund Olesen2012-06-261-1/+5
| | | | | | | | Such passes can be used to tweak the register assignments in a target-dependent way, for example to avoid write-after-write dependencies. llvm-svn: 159209
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-269-9/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* Replacing zero-sized alloca's with a null pointer is too aggressive, insteadDuncan Sands2012-06-261-8/+40
| | | | | | | | | | | | | | | | merge all zero-sized alloca's into one, fixing c43204g from the Ada ACATS conformance testsuite. What happened there was that a variable sized object was being allocated on the stack, "alloca i8, i32 %size". It was then being passed to another function, which tested that the address was not null (raising an exception if it was) then manipulated %size bytes in it (load and/or store). The optimizers cleverly managed to deduce that %size was zero (congratulations to them, as it isn't at all obvious), which made the alloca zero size, causing the optimizers to replace it with null, which then caused the check mentioned above to fail, and the exception to be raised, wrongly. Note that no loads and stores were actually being done to the alloca (the loop that does them is executed %size times, i.e. is not executed), only the not-null address check. llvm-svn: 159202
* Removed unused variableElena Demikhovsky2012-06-261-1/+0
| | | | llvm-svn: 159197
* Rename to match other X86_64* names.Bill Wendling2012-06-263-5/+5
| | | | llvm-svn: 159196
* Shuffle optimization for AVX/AVX2.Elena Demikhovsky2012-06-261-0/+52
| | | | | | | | | | | | | | | | | | The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction. Before: vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3] vextractf128 $1, %ymm1, %xmm1 vextractf128 $1, %ymm0, %xmm0 vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3] vinsertf128 $1, %xmm0, %ymm2, %ymm0 After: vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4] vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4] vunpcklps %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] llvm-svn: 159188
* Update a bunch of stale comments that dated from when this folled theChandler Carruth2012-06-261-14/+11
| | | | | | | very first (and worst) placement algorithm. These should now more accurately reflect the reality of the pass. llvm-svn: 159185
* Remove some duplicate instructions that exist only to given different ↵Craig Topper2012-06-261-16/+13
| | | | | | mnemonics for the assembler. Use InstAlias instead. llvm-svn: 159184
* Enable the new LoopInfo algorithm by default.Andrew Trick2012-06-263-20/+9
| | | | | | | | | | | | | | | | | | | | | | | | The primary advantage is that loop optimizations will be applied in a stable order. This helps debugging and unit test creation. It is also a better overall implementation without pathologically bad performance on deep functions. On large functions (llvm-stress --size=200000 | opt -loops) Before: 0.1263s After: 0.0225s On deep functions (after tweaking llvm-stress, thanks Nadav): Before: 0.2281s After: 0.0227s See r158790 for more comments. The loop tree is now consistently generated in forward order, but loop passes are applied in reverse order over the program. If we have a loop optimization that prefers forward order, that can easily be achieved by adding a different type of LoopPassManager. llvm-svn: 159183
* Remove unnecessary FIXMEAndrew Trick2012-06-261-3/+0
| | | | llvm-svn: 159182
* Make sure type is not extended or untyped before create a constant of the ↵Evan Cheng2012-06-261-0/+4
| | | | | | type. No test case. Found by inspection. llvm-svn: 159179
* Make some ugly hacks for inline asm operands which name a specific register ↵Eli Friedman2012-06-251-2/+5
| | | | | | a bit more thorough. PR13196. llvm-svn: 159176
* revert my previous commit (r159173), since as Eli pointed out, it's ↵Nuno Lopes2012-06-251-0/+1
| | | | | | perfectly ok to mark realloc as noalias llvm-svn: 159175
* do not set realloc() as NotAlias, since it can return the same pointer. This ↵Nuno Lopes2012-06-251-1/+0
| | | | | | whole thing should be upgraded to use the MemoryBuiltin interface anyway.. llvm-svn: 159173
* ARM: update peephole optimization.Manman Ren2012-06-251-2/+18
| | | | | | | | | | More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 llvm-svn: 159166
* Fix the objc_autoreleasedReturnValue optimization code to locateDan Gohman2012-06-251-2/+17
| | | | | | | the call correctly even in the case where it is an invoke. This fixes rdar://11714057. llvm-svn: 159157
* Enforce stricter liveness rules for PHIs.Jakob Stoklund Olesen2012-06-251-6/+11
| | | | | | | | | | | | | Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. llvm-svn: 159150
* Run ProcessImplicitDefs on SSA form where it can be much simpler.Jakob Stoklund Olesen2012-06-252-262/+99
| | | | | | | | | | | Implicitly defined virtual registers can simply have the <undef> bit set on all uses, and copies can be turned into implicit defs recursively. Physical registers are a bit trickier. We handle the common case where a physreg def is used by a nearby instruction in the same basic block. For more complicated cases, just leave the IMPLICIT_DEF instruction in. llvm-svn: 159149
* improve optimization of invoke instructions:Nuno Lopes2012-06-253-4/+17
| | | | | | | | - simplifycfg: invoke undef/null -> unreachable - instcombine: invoke new -> invoke expect(0, 0) (an arbitrary NOOP intrinsic; only done if the allocated memory is unused, of course) - verifier: allow invoke of intrinsics (to make the previous step work) llvm-svn: 159146
* check for the NoAlias attribute through CallSiteNuno Lopes2012-06-251-2/+2
| | | | llvm-svn: 159145
* PR13013: ELF Type identification fails for MSB type ELF files.Meador Inge2012-06-251-2/+5
| | | | | | | | | Fix 'sys::IdentifyFileType' to work with big and little endian byte orderings when reading the ELF object file type. Initial patch by Stefan Hepp. llvm-svn: 159138
* If a constant or a function has linkonce_odr linkage and unnamed_addr, mark itRafael Espindola2012-06-251-0/+11
| | | | | | | | hidden. Being linkonce_odr guarantees that it is available in every dso that needs it. Being a constant/function with unnamed_addr guarantees that the copies don't have to be merged. llvm-svn: 159136
* The name (and comment describing) of llvm::GetFirstDebuigLocInBasicBlock no ↵Eli Bendersky2012-06-252-11/+5
| | | | | | longer represents what the function does. Therefore, the function is removed and its functionality is folded into the only place in the code-base where it was being used. llvm-svn: 159133
* Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because ↵Craig Topper2012-06-251-0/+3
| | | | | | there are no patterns in the instruction. llvm-svn: 159127
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