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* don't repeat names in comments ; NFCSanjay Patel2016-01-131-5/+5
| | | | llvm-svn: 257643
* fix typoSanjay Patel2016-01-131-1/+1
| | | | llvm-svn: 257626
* AMDGPU/SI: Fix a GPU hang with POS_W_FLOAT enabledMarek Olsak2016-01-131-1/+8
| | | | | | | | | | Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16037 llvm-svn: 257625
* AMDGPU/SI: Remove ending s_endpgm from non-void functionsMarek Olsak2016-01-131-0/+8
| | | | | | | | | | Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16035 llvm-svn: 257623
* AMDGPU/SI: Add s_waitcnt at the end of non-void functionsMarek Olsak2016-01-134-1/+19
| | | | | | | | | | | | | | Summary: v2: Make ReturnsVoid private, so that I can another 8 lines of code and look more productive. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16034 llvm-svn: 257622
* AMDGPU/SI: Add support for non-void functionsMarek Olsak2016-01-136-1/+136
| | | | | | | | | | | | | | | | | | | Summary: Return values can be stored in SGPRs (i32) and VGPRs (f32). This will be used by functions which expect some bytecode or other binary to be appended at the end. It allows defining in which registers the return values will be stored. v2: don't do this for compute shaders Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16033 llvm-svn: 257621
* [WebAssemly] Invalidate liveness in CFG stackifierDerek Schuff2016-01-131-0/+3
| | | | | | | WebAssemblyCFGStackify does not track liveness for EXPR_STACK, causing verifier failure if liveness has not already been invalidated. llvm-svn: 257620
* fix typoSanjay Patel2016-01-131-1/+1
| | | | llvm-svn: 257613
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-139-3/+2503
| | | | | | | | | | | | | | | | Summary: It is off by default, but can be used with --misched=si Patch by: Axel Davy Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: nhaehnle, solenskiner, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D11885 llvm-svn: 257609
* Fixing warning by adding the X86ISD::VROTRI case. Michael Zuckerman2016-01-131-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D16052 llvm-svn: 257607
* [Hexagon] Do not insert non-phis before phis in bit simplificationKrzysztof Parzyszek2016-01-131-7/+19
| | | | llvm-svn: 257606
* [AVX512] Adding PMOVSXBD/W/Q , PMOVZSDQ and PMOVZSWD/Q Intrinsics .Michael Zuckerman2016-01-131-0/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D16111 llvm-svn: 257604
* [AVX512] Adding PMOVZXBD/W/Q , PMOVZXDQ and PMOVZXWD/Q Intrinsics Michael Zuckerman2016-01-131-0/+36
| | | | | | Differential Revision:http://reviews.llvm.org/D16071 llvm-svn: 257601
* [PowerPC] Fix large code model with the ELFv2 ABIUlrich Weigand2016-01-133-24/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The global entry point prologue currently assumes that the TOC associated with a function is less than 2GB away from the function entry point. This is always true when using the medium or small code model, but may not be the case when using the large code model. This patch adds a new variant of the ELFv2 global entry point prologue that lifts the 2GB restriction when building with -mcmodel=large. This works by emitting a quadword containing the distance from the function entry point to its associated TOC immediately before the entry point, and then using a prologue like: ld r2,-8(r12) add r2,r2,r12 Since creation of the entry point prologue is now split across two separate routines (PPCLinuxAsmPrinter::EmitFunctionEntryLabel emits the data word, PPCLinuxAsmPrinter::EmitFunctionBodyStart the prolog code), I've switched to using named labels instead of just temporaries to indicate the locations of the global and local entry points and the new TOC offset data word. These names are provided by new routines in PPCFunctionInfo modeled after the existing PPCFunctionInfo::getPICOffsetSymbol. Note that a corresponding change was committed to GCC here: https://gcc.gnu.org/ml/gcc-patches/2015-12/msg00355.html Reviewers: hfinkel Differential Revision: http://reviews.llvm.org/D15500 llvm-svn: 257597
* [AVX512] adding PRORQ , PRORD , PRORLVQ and PRORLVD Intrinsics Michael Zuckerman2016-01-134-3/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D16052 llvm-svn: 257594
* AMDGPU/SI: Allow more shader inputsMarek Olsak2016-01-131-6/+30
| | | | | | | | | | Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16032 llvm-svn: 257593
* AMDGPU/SI: Allow any number of PS inputsMarek Olsak2016-01-131-3/+1
| | | | | | | | | | | | | | Summary: With the ability to concatenate shader binaries, the limit of 15 no longer applies. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16031 llvm-svn: 257592
* AMDGPU/SI: Add new target attribute InitialPSInputAddrMarek Olsak2016-01-137-15/+55
| | | | | | | | | | | | | | | | | | | | | Summary: This allows Mesa to pass initial SPI_PS_INPUT_ADDR to LLVM. The register assigns VGPR locations to PS inputs, while the ENA register determines whether or not they are loaded. Mesa needs to set some inputs as not-movable, so that a pixel shader prolog binary appended at the beginning can assume where some inputs are. v2: Make PSInputAddr private, because there is never enough silly getters and setters for people to read. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16030 llvm-svn: 257591
* AMDGPU/SI: Fix a bug in SIFoldOperandsMarek Olsak2016-01-131-0/+11
| | | | | | | | | | | | Summary: ret.ll will contain a test for this Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16029 llvm-svn: 257590
* LEA code size optimization pass (Part 2): Remove redundant LEA instructions.Andrey Turetskiy2016-01-132-3/+160
| | | | | | | | | | Make x86 OptimizeLEAs pass remove LEA instruction if there is another LEA (in the same basic block) which calculates address differing only be a displacement. Works only for -Oz. Differential Revision: http://reviews.llvm.org/D13295 llvm-svn: 257589
* Remove extra whitespace. NFC.Junmo Park2016-01-131-10/+10
| | | | llvm-svn: 257578
* [SPARC] Revamp AnalyzeBranch and add ReverseBranchCondition.James Y Knight2016-01-132-89/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AnalyzeBranch on X86 (and, previously, SPARC, which implementation was copied from X86) tries to modify the branches based on block layout (e.g. checking isLayoutSuccessor), when AllowModify is true. The rest of the architectures leave that up to the caller, which can call InsertBranch, RemoveBranch, and ReverseBranchCondition as appropriate. That appears to be the preferred way to do it nowadays. This commit makes SPARC like the rest: replaces AnalyzeBranch with an implementation cribbed from AArch64, and adds a ReverseBranchCondition implementation. Additionally, a test-case has been added (also cribbed from AArch64) demonstrating that redundant branch sequences no longer get emitted. E.g., it used to emit code like this: bne .LBB1_2 nop ba .LBB1_1 nop .LBB1_2: And now emits: cmp %i0, 42 be .LBB1_1 nop llvm-svn: 257572
* [Coverage] Refactor coverage mapping reader code Xinliang David Li2016-01-131-17/+13
| | | | | | | | | | | | | | (Resubmit after fixing a typo that breaks test on big endian machines) In this refactoring, member functions are introduced to access CovMap header/func record members and hide layout details. This will enable further code restructuring to support reading multiple versions of coverage mapping data with shared/templatized code. (When coveremap format version changes, backward compatibtility should be preserved). llvm-svn: 257571
* Rollback r257551 -- unexpected test failures TBIXinliang David Li2016-01-131-13/+17
| | | | llvm-svn: 257564
* Re-Revert r257105 (Verifier debug info changes)Keno Fischer2016-01-132-64/+16
| | | | | | | While I investigate some new buildbot failures. This was originally reapplied as r257550 and r257558. llvm-svn: 257563
* [libFuzzer] make sure to update CurrentUnit when drillingKostya Serebryany2016-01-131-1/+4
| | | | llvm-svn: 257560
* Use utostr rather than std::to_stringKeno Fischer2016-01-131-2/+2
| | | | | | | Looks like std::to_string is not available for Android. Hopefully this fixes the bot. llvm-svn: 257558
* AsmPrinter: Fix wrong OS X versions being emitted for darwin triplesMatthias Braun2016-01-131-14/+18
| | | | | | | | | | | | The version numbers of the darwin kernel are different from the version numbers of OS X, so we need adjustments if we had "*-*-darwin" triples. Use the existing utility functions in TargetTriple for this. Fixes rdar://22056966 Differential Revision: http://reviews.llvm.org/D14601 llvm-svn: 257555
* [CodeView] Mark our lines as statements, not expressionsDavid Majnemer2016-01-131-3/+18
| | | | | | | | | The line tables for CodeView make a distinction between expressions and statements. As it turns out, MSVC always emits them as statements and we always emit them as expressions. Let's switch to statements to match the CodeView that they emit. llvm-svn: 257553
* [Coverage] Refactor coverage mapping reader code /NFCXinliang David Li2016-01-131-17/+13
| | | | | | | | | | | | | (Resubmit after fixing build bot failures) In this refactoring, member functions are introduced to access CovMap header/func record members and hide layout details. This will enable further code restructuring to support reading multiple versions of coverage mapping data with shared/templatized code. (When coveremap format version changes, backward compatibtility should be preserved). llvm-svn: 257551
* Reapply r257105 "[Verifier] Check that debug values have proper size"Keno Fischer2016-01-132-16/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The follow extra changes were made to test cases: Manually making the variable be the actual type instead of a pointer to avoid pointer-size differences in generic code: LLVM :: DebugInfo/Generic/2010-03-24-MemberFn.ll LLVM :: DebugInfo/Generic/2010-04-06-NestedFnDbgInfo.ll LLVM :: DebugInfo/Generic/2010-05-03-DisableFramePtr.ll LLVM :: DebugInfo/Generic/varargs.ll Delete sizing information from debug info for the same reason (but the presence of the pointer was important to the test case): LLVM :: DebugInfo/Generic/restrict.ll LLVM :: DebugInfo/Generic/tu-composite.ll LLVM :: Linker/type-unique-type-array-a.ll LLVM :: Linker/type-unique-simple2.ll Fixing an incorrect DW_OP_deref LLVM :: DebugInfo/Generic/2010-05-03-OriginDIE.ll Fixing a missing DW_OP_deref LLVM :: DebugInfo/Generic/incorrect-variable-debugloc.ll Additionally, clang should no longer complain during bootstrap should no longer happen after r257534. The original commit message was: ``` Summary: Teach the Verifier to make sure that the storage size given to llvm.dbg.declare or the value size given to llvm.dbg.value agree with what is declared in DebugInfo. This is implicitly assumed in a number of passes (e.g. in SROA). Additionally this catches a number of common mistakes, such as passing a pointer when a value was intended or vice versa. One complication comes from stack coloring which modifies the original IR when it merges allocas in order to make sure that if AA falls back to the IR it gets the correct result. However, given this new invariant, indiscriminately replacing one alloca by a different (differently sized one) is no longer valid. Fix this by just undefing out any use of the alloca in a dbg.declare in this case. Additionally, I had to fix a number of test cases. Of particular note: - I regenerated dbg-changes-codegen-branch-folding.ll from the given source as it was affected by the bug fixed in r256077 - two-cus-from-same-file.ll was changed to avoid having a variable-typed debug variable as that would depend on the target, even though this test is supposed to be generic - I had to manually declared size/align for reference type. See also the discussion for D14275/r253186. - fpstack-debuginstr-kill.ll required changing `double` to `long double` - most others were just a question of adding OP_deref ``` llvm-svn: 257550
* Rollback r257547 -- buildbot failure TBIXinliang David Li2016-01-131-13/+17
| | | | llvm-svn: 257549
* [Coverage] Refactor coverage mapping reader code /NFCXinliang David Li2016-01-131-17/+13
| | | | | | | | | | | In this refactoring, member functions are introduced to access CovMap header/func record members and hide layout details. This will enable further code restructuring to support reading multiple versions of coverage mapping data with shared/templatized code. (When coveremap format version changes, backward compatibtility should be preserved). llvm-svn: 257547
* Guard fabs to bfc convert with V6T2 flagAna Pazos2016-01-131-2/+2
| | | | | | | | | | | | | | Summary: BFC instructions are available in ARMv6T2 and above. Reviewers: t.p.northover Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D16076 llvm-svn: 257546
* [ARM] Mark VMOV with immediate: isAsCheapAsMove.Quentin Colombet2016-01-131-2/+5
| | | | | | | | | | VMOVs are not strictly speaking cheap, but they are as expensive as a vector copy (VORR), so we should prefer rematerialization over splitting when it applies. rdar://problem/23754176 llvm-svn: 257545
* CannotBeOrderedLessThanZero: add some missing casesFiona Glaser2016-01-121-0/+12
| | | | llvm-svn: 257542
* COFF: Teach llvm-objdump how to dump DLL forwarder symbols.Rui Ueyama2016-01-121-0/+24
| | | | llvm-svn: 257539
* [WebAssembly] Fix disassembler shared-libs buildDerek Schuff2016-01-121-1/+2
| | | | llvm-svn: 257536
* RegisterPressure: Expose RegisterOperands APIMatthias Braun2016-01-122-65/+65
| | | | | | | | | | | | | | | | | | | | | | Previously the RegisterOperands have only been used internally in RegisterPressure.cpp. However this datastructure can be useful for other tasks as well and allows refactoring of PDiff initialisation out of RPTracker::recede(). This patch: - Exposes RegisterOperands as public API - Splits RPTracker::recede() into a part that skips DebugValues and maintains the region borders, and the core that changes register pressure when given a set of RegisterOperands. - This allows to move the PDiff initialisation out recede() into a method of the PressureDiffs class. - The upcoming subregister scheduling code will also use RegisterOperands to avoid pushing more unrelated functionality into recede()/advance(). Differential Revision: http://reviews.llvm.org/D15473 llvm-svn: 257535
* [Utils] Insert DW_OP_bit_piece when only describing part of the variableKeno Fischer2016-01-121-2/+24
| | | | | | | | | | | | | Summary: The dbg.declare -> dbg.value conversion looks through any zext/sext to find a value to describe the variable (in the expectation that those zext/sext instruction will go away later). However, those values do not cover the entire variable and thus need a DW_OP_bit_piece. Reviewers: aprantl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D16061 llvm-svn: 257534
* [Support] Add saturating multiply-add support functionNathan Slingerland2016-01-121-14/+3
| | | | | | | | | | | | Summary: Add SaturatingMultiplyAdd convenience function template since A + (X * Y) comes up frequently when doing weighted arithmetic. Reviewers: davidxl, silvas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15385 llvm-svn: 257532
* [CodeView] Initialize column-end to zeroDavid Majnemer2016-01-121-1/+1
| | | | | | | | | | | | | CodeView, unlike DWARF, can associate code with a range of columns. However, LLVM can only represent a single column position internally. We used to claim that the end column and start column were the same which yielded less than satisfactory results: we would stop printing at the _beginning_ of the source expression! Instead, mark the column-end as 'zero' to indicate that we don't have one (as per the documentation for IDiaLineNumber::get_lineNumberEnd). llvm-svn: 257528
* [WebAsssembly] Register the MC register info.Dan Gohman2016-01-121-0/+9
| | | | llvm-svn: 257525
* [AVX512] adding PROLQ and PROLD IntrinsicsMichael Zuckerman2016-01-125-1/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D16048 llvm-svn: 257523
* Codegen: [PPC] Handle weighted comparisons when inserting selects.Kyle Butt2016-01-121-10/+33
| | | | | | | | | | | | | Only non-weighted predicates were handled in PPCInstrInfo::insertSelect. Handle the weighted predicates as well. This latent bug was triggered by r255398, because it added use of the branch-weighted predicates. While here, switch over an enum instead of an int to get the compiler to enforce totality in the future. llvm-svn: 257518
* [WebAssembly] Add a EM_WEBASSEMBLY value, and several bits of code that use it.Dan Gohman2016-01-123-5/+10
| | | | | | | | | A request has been made to the official registry, but an official value is not yet available. This patch uses a temporary value in order to support development. When an official value is recieved, the value of EM_WEBASSEMBLY will be updated. llvm-svn: 257517
* [WebAssembly] Introduce a WebAssemblyTargetStreamer class.Dan Gohman2016-01-129-64/+225
| | | | | | | Refactor .param, .result, .local, and .endfunc, as directives, using the proper MCTargetStreamer mechanism, rather than fake instructions. llvm-svn: 257511
* Replace inherited constructor with an explicit oneKrzysztof Parzyszek2016-01-121-2/+2
| | | | | | Some bots failed when the inherited constructor was used. llvm-svn: 257508
* [WebAssembly] Make CFG stackification independent of basic-block labels.Dan Gohman2016-01-128-82/+161
| | | | | | | | | | | | | | | | | | | | | | | This patch changes the way labels are referenced. Instead of referencing the basic-block label name (eg. .LBB0_0), instructions now just have an immediate which indicates the depth in the control-flow stack to find a label to jump to. This makes them much closer to what we expect to have in the binary encoding, and avoids the problem of basic-block label names not being explicit in the binary encoding. Also, it terminates blocks and loops with end_block and end_loop instructions, rather than basic-block label names, for similar reasons. This will also fix problems where two constructs appear to have the same label, because we no longer explicitly use labels, so consumers that need labels will presumably create their own labels, and presumably they won't reuse labels when they do. This patch does make the code a little more awkward to read; as a partial mitigation, this patch also introduces comments showing where the labels are, and comments on each branch showing where it's branching to. llvm-svn: 257505
* [Hexagon] Implement RDF-based post-RA optimizationsKrzysztof Parzyszek2016-01-125-2/+372
| | | | | | | | - Handle simple cases of register copies (what current RDF CP allows). - Hexagon-specific dead code elimination: handles dead address updates in post-increment instructions. llvm-svn: 257504
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