|  | Commit message (Collapse) | Author | Age | Files | Lines | 
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| | llvm-svn: 109956 | 
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| | like my instcombine patch.", in an attempt to fix Clang i386 bootstrap.
 - Also PR7719.
llvm-svn: 109953 | 
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| | llvm-svn: 109949 | 
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| | the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.
llvm-svn: 109948 | 
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| | llvm-svn: 109947 | 
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| | llvm-svn: 109946 | 
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| | exactly what bugpoint expected it to do.
There was also only one user of
BlockExtractorPass(const std::vector<BasicBlock*> &B), so just remove it and
make BlockExtractorPass read BlockFile.
This fixes bugpoint's block extraction.
Nick, please review.
llvm-svn: 109936 | 
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| | involves rolling back some
of my earlier data structure improvements until I can ensure that there are no iterator invalidation problems.
llvm-svn: 109935 | 
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| | shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues.
llvm-svn: 109934 | 
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| | reference registers past the end of the NEON register file, and report them
as invalid instead of asserting when trying to print them.  PR7746.
llvm-svn: 109933 | 
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| | formerly rejected by the FE, so asserted in the BE; now the FE only
warns, so we treat it as a legitimate fatal error in PPC BE.
This means the test for the feature won't pass, so it's xfail'd.
llvm-svn: 109892 | 
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| | llvm-svn: 109891 | 
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| | miscompilation in.
llvm-svn: 109889 | 
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| | llvm-svn: 109886 | 
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| | beginning on ARM Darwin assembly files so that it won't be placed after
debug sections.  Radar 8252813.
llvm-svn: 109879 | 
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| | declared during the addition of the assembler support, the additional
changes are:
- Add missing intrinsics
- Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file.
- Duplicate some patterns to AVX mode.
- Step into PCMPEST/PCMPIST custom inserter and add AVX versions.
llvm-svn: 109878 | 
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| | llvm-svn: 109877 | 
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| | llvm-svn: 109875 | 
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| | llvm-svn: 109872 | 
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| | check the range of the constant when optimizing a comparison between a
constant and a sign_extend_inreg node.
llvm-svn: 109854 | 
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| | have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
llvm-svn: 109842 | 
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| | llvm-svn: 109813 | 
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| | transformations.
llvm-svn: 109800 | 
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| | integers with mov + vdup.  8003375.  This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).
llvm-svn: 109799 | 
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| | PR7745.
llvm-svn: 109788 | 
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| | if CExpr is a ConstantInt.
llvm-svn: 109773 | 
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| | the QADD & QSUB instructions.
Behave identically to __qadd & __qsub RealView instruction intrinsics.
llvm-svn: 109770 | 
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| | ownership of the TargetAsmBackend and the MCCodeEmitter.
llvm-svn: 109767 | 
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| | llvm-svn: 109765 | 
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| | We do sometimes load from a too small stack slot when dealing with x86 arguments
(varargs and smaller-than-32-bit args). It looks like we know what we are doing
in those cases, so I am going to remove the assert instead of artifically
enlarging stack slot sizes.
The assert in storeRegToStackSlot stays in. We don't want to write beyond the
bounds of a stack slot.
llvm-svn: 109764 | 
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| | llvm-svn: 109752 | 
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| | llvm-svn: 109746 | 
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| | llvm-svn: 109745 | 
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| | llvm-svn: 109721 | 
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| | llvm-svn: 109720 | 
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| | angst.
llvm-svn: 109718 | 
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| | - This works, but won't handle crashes on stack overflow, or signals delivered
   to a thread other than the one that crashed. The latter is particular annoying
   on Darwin, because SIGABRT tends to go to the main thread.
llvm-svn: 109717 | 
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| | multiple defs, like t2LDRSB_POST.
The first def could accidentally steal the physreg that the second, tied def was
required to be allocated to.
Now, the tied use-def is treated more like an early clobber, and the physreg is
reserved before allocating the other defs.
This would never be a problem when the tied def was the only def which is the
usual case.
This fixes MallocBench/gs for thumb2 -O0.
llvm-svn: 109715 | 
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| | extend it to handle the case where multiple RAUWs affect a single
SCEVUnknown.
Add a ScalarEvolution unittest to test for this situation.
llvm-svn: 109705 | 
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| | for supporting PHI translation.
llvm-svn: 109701 | 
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| | UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
llvm-svn: 109696 | 
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| | input shift was actually a rotate. rdar://8240138
llvm-svn: 109693 | 
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| | llvm-svn: 109691 | 
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| | from the tree
llvm-svn: 109687 | 
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| | llvm-svn: 109686 | 
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| | initialize a new set of maps on every query.
llvm-svn: 109679 | 
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| | alignment, fixing silent truncation of alignment values.
llvm-svn: 109653 | 
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| | The size of this object isn't used for anything - technically it is of variable
size.
This avoids a false positive from the assert in
X86InstrInfo::loadRegFromStackSlot, and fixes PR7735.
llvm-svn: 109652 | 
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| | the info from the .file directive and makes file and directory tables that
will eventually be put out as part of the dwarf info in the output file.
llvm-svn: 109651 | 
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| | llvm-svn: 109650 |