| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 77920
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pushes in the function prolog if the function doesn't have any stack space,
i.e. for a prolog like:
0x40011870: push %r15
0x40011872: push %r14
0x40011874: push %rbx
Patch by Zoltan!
llvm-svn: 77919
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Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
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__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.
__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.
We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.
llvm-svn: 77917
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llvm-svn: 77914
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llvm-svn: 77913
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not been spilled.
llvm-svn: 77912
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llvm-svn: 77911
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llvm-svn: 77907
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instruction.
llvm-svn: 77906
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Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier.
Allow redefinition of a sub-register of a live register.
llvm-svn: 77904
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llvm-svn: 77903
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This is just the framework to identify the needed workarounds. They are not actually implemented.
llvm-svn: 77902
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We use the same constraints as GCC, including those that are slightly insane for inline assembler.
llvm-svn: 77899
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Generate code for the Blackfin family of DSPs from Analog Devices:
http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
We aim to be compatible with the exsisting GNU toolchain found at:
http://blackfin.uclinux.org/gf/project/toolchain
The back-end is experimental.
llvm-svn: 77897
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support. This isn't immediately interesting, because Legalize
ends up lowering SELECT_CC if the target doesn't support it,
but this simplifies the process.
Also, if the SELECT_CC would be expanded in Legalize, it
can potentially end up with two copies of the condition
expression. By leaving it as SELECT+SETCC, the SELECT can be
expanded into two SELECTs that use a single SETCC.
The two comparisons are usually CSE'd, but depending on
when various expressions get legalized, the comparison
expression could involve calls to library functions, such
that the comparison expression may not be able to be CSE'd.
This will be needed by a future patch.
llvm-svn: 77896
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llvm-svn: 77895
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llvm-svn: 77894
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llvm-svn: 77893
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llvm-svn: 77892
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Use of an <undef> register is treated like an <imp-use>. It is not an error to use a dead <undef> register.
llvm-svn: 77890
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TLOF, unifying all the dwarf targets at the same time.
llvm-svn: 77889
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llvm-svn: 77888
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object files.
llvm-svn: 77887
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llvm-svn: 77878
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the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
llvm-svn: 77877
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in a header.
llvm-svn: 77874
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llvm-svn: 77873
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llvm-svn: 77872
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llvm-svn: 77871
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llvm-svn: 77869
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llvm-svn: 77868
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llvm-svn: 77867
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defaults to being ELF.
llvm-svn: 77866
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solaris :)
llvm-svn: 77865
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llvm-svn: 77864
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no longer depends on TM!
llvm-svn: 77863
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llvm-svn: 77861
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llvm-svn: 77859
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llvm-svn: 77858
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even considering #if 0 code.
llvm-svn: 77856
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behavior of the LSDA section instead of on some random target hook that
needs to be kept in synch with other points of truth.
llvm-svn: 77855
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getLSDASection() to be more specific. This makes it pretty obvious
that the ELF LSDA section is being specified wrong in PIC mode. We're
probably getting a lot of startup-time relocations to a readonly page,
which is expensive and bad.
Someone who cares about ELF C++ should investigate this.
llvm-svn: 77847
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llvm-svn: 77846
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variables either.
llvm-svn: 77844
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declaration will end up in.
llvm-svn: 77843
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TAI.
llvm-svn: 77842
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llvm-svn: 77838
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operands.
llvm-svn: 77837
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llvm-svn: 77835
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