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* [ORC] Coalesce all of ORC's symbol renaming / linkage-promotion utilities intoLang Hames2018-09-272-50/+16
| | | | | | | | | | | | one SymbolLinkagePromoter utility. SymbolLinkagePromoter renames anonymous and private symbols, and bumps all linkages to at least global/hidden-visibility. Modules whose symbols have been promoted by this utility can be decomposed into sub-modules without introducing link errors. This is used by the CompileOnDemandLayer to extract single-function modules for lazy compilation. llvm-svn: 343257
* AMDGPU/NFC: Simplify VOP_MAC_F16/F32Konstantin Zhuravlyov2018-09-271-11/+2
| | | | llvm-svn: 343254
* [AMDGPU] Fold copy (copy vgpr)Stanislav Mekhanoshin2018-09-271-0/+14
| | | | | | | | This allows to reduce a number of used VGPRs in some cases. Differential Revision: https://reviews.llvm.org/D52577 llvm-svn: 343249
* [ScalarizeMaskedMemIntrin] Don't emit 'icmp eq i1 %x, 1' to check mask ↵Craig Topper2018-09-271-23/+9
| | | | | | | | values. That's just %x so use that directly. Had we emitted this IR earlier, InstCombine would have removed icmp so I'm going to assume using the i1 directly would be considered canonical. llvm-svn: 343244
* [X86] Remove BT/BTC/BTR/BTS rr/ri overridesSimon Pilgrim2018-09-271-4/+3
| | | | llvm-svn: 343241
* [X86][Btver2] (V)MPSADBW instructions take 3uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343238
* Revert r343192 as an ubsan build is currently failingLuke Cheeseman2018-09-2714-82/+10
| | | | llvm-svn: 343235
* [X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343234
* [X86] Split BT and BTC/BTR/BTS scheduler classesSimon Pilgrim2018-09-2711-28/+33
| | | | llvm-svn: 343233
* [Sparc] EXPENSIVE_CHECKS now passes all machine verifier errors (PR27461)Simon Pilgrim2018-09-271-4/+0
| | | | | | | | Now that D51487 has landed, the last machine verifier tests that failed EXPENSIVE_CHECKS builds have now been fixed/removed, so we can remove @MatzeB 's isMachineVerifierClean() hack for sparc targets. Differential Revision: https://reviews.llvm.org/D52612 llvm-svn: 343232
* [AArch64] Refactor immediate details out of add/sub tblgen class (NFCI)Oliver Stannard2018-09-271-13/+19
| | | | | | | | | | | | | | Bits [23-22] are used in Add and Sub to specify the shift. The value of the shift field must be 0x; values of 1x are unallocated. MTE adds some instructions that use such encodings, and this patch refactors the Add/Sub class so that another class could derive from this one to implement other encodings and other formats of bitfields. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52489 llvm-svn: 343231
* [AArch64][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-271-0/+2
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52483 llvm-svn: 343229
* [InstCombine] Without infinites, fold (C / X) < 0.0 --> (X < 0)Sanjay Patel2018-09-271-0/+55
| | | | | | | | | | | | | | | | | | | | When C is not zero and infinites are not allowed (C / X) > 0 is a sign test. Depending on the sign of C, the predicate must be swapped. E.g.: foo(double X) { if ((-2.0 / X) <= 0) ... } => foo(double X) { if (X >= 0) ... } Patch by: @marels (Martin Elshuber) Differential Revision: https://reviews.llvm.org/D51942 llvm-svn: 343228
* [X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT)Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343227
* [WPD] Fix incorrect devirtualization after indirect call promotionTeresa Johnson2018-09-273-46/+80
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a dominance check to ensure that the possible devirtualizable call is actually dominated by the type test/checked load intrinsic being analyzed. With PGO, after indirect call promotion is performed during the compile step, followed by inlining, we may have a type test in the promoted and inlined sequence that allows an indirect call in that sequence to be devirtualized. That indirect call (inserted by inlining after promotion) will share the same vtable pointer as the fallback indirect call that cannot be devirtualized. Before this patch the code was incorrectly devirtualizing the fallback indirect call. See the new test and the example described there for more details. Reviewers: pcc, vitalybuka Subscribers: mehdi_amini, Prazek, eraman, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D52514 llvm-svn: 343226
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-2710-1/+139
| | | | | | | | | | | | This adds new instructions used by the Branch Target Identification feature. When this is enabled, these are the only instructions which can be targeted by indirect branch instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52485 llvm-svn: 343225
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-276-5/+32
| | | | | | | | | | | This adds some new system registers which can be used to restrict certain types of speculative execution. Patch by Pablo Barrio and David Spickett! Differential revision: https://reviews.llvm.org/D52482 llvm-svn: 343218
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-273-0/+12
| | | | | | | | | | | | | This adds two new system registers, used to generate random numbers. This is an optional extension to v8.5-A, and will be controlled by the "+rng" modifier of the -march= and -mcpu= options. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52481 llvm-svn: 343217
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-276-2/+13
| | | | | | | | | | | This adds a new variant of the DC system instruction for persistent memory. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52480 llvm-svn: 343216
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-278-4/+89
| | | | | | | | | | | | This adds new system instructions which act as barriers to speculative execution based on earlier execution within a particular execution context. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52479 llvm-svn: 343214
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-275-2/+32
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52477 llvm-svn: 343213
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-273-2/+17
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52476 llvm-svn: 343211
* [Sparc] Remove the support for builtin setjmp/longjmpDaniel Cederman2018-09-273-270/+0
| | | | | | | | | | | | | | | | Summary: It is currently broken and for Sparc there is not much benefit in using a builtin version compared to a library version. Both versions needs to store the same four values in setjmp and flush the register windows in longjmp. If the need for a builtin setjmp/longjmp arises there is an improved implementation available at https://reviews.llvm.org/D50969. Reviewers: jyknight, joerg, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D51487 llvm-svn: 343210
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-274-3/+63
| | | | | | | | | | | | These are some new variants of the "Floating-point Round to Integral" family of instructions, which round to the nearest floating-point value which fits in a 32- or 64-bit integer. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52475 llvm-svn: 343209
* [Sparc] Add unimp aliasDaniel Cederman2018-09-271-0/+3
| | | | | | | | | | | | | Summary: Use 0 as the default immediate for the UNIMP instruction. This matches the behavior in gas. Reviewers: jyknight, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D51526 llvm-svn: 343203
* [Sparc] Add support for the partial write PSR instructionDaniel Cederman2018-09-275-1/+26
| | | | | | | | | | | | | | | Summary: Partial write %PSR (WRPSR) is a SPARC V8e option that allows WRPSR instructions to only affect the %PSR.ET field. It is supported by the GR740 and GR716. Reviewers: jyknight, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48644 llvm-svn: 343202
* [X86][Btver2] TZCNT instructions take 2uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343200
* [PowerPC] [NFC] Refactor code for printing register operandsNemanja Ivanovic2018-09-276-77/+72
| | | | | | | | | | | | | | | | | | | | | | | We have an unfortunate situation in our back end where we have to keep pairs of functions synchronized. Needless to say that this is not an ideal situation as it is very difficult to enforce. Even without bugs, it's annoying to have to do the same thing in two places. This patch just refactors the code so that the two pairs of those functions that pertain to printing register operands are unified: - stripRegisterPrefix() - this just removes the letter prefixes from registers for the InstrPrinter and AsmPrinter. This patch provides this as a static member of PPCRegisterInfo - Handling of PPCII::UseVSXReg - there are 3 places where we do something special for instructions with that flag set. Each of those places does its own checking of this flag and implements code customization. Any changes to how we print/encode VSX/VMX registers require modifying all 3 places. This patch unifies this into a static function in PPCInstrInfo that returns the register number adjusted as needed. Differential revision: https://reviews.llvm.org/D52467 llvm-svn: 343195
* [X86][Btver2] Add uops counter for exegesis reportsSimon Pilgrim2018-09-271-0/+1
| | | | llvm-svn: 343194
* Reapply changes reverted in r343114, lldb patch to follow shortlyLuke Cheeseman2018-09-2714-10/+82
| | | | llvm-svn: 343192
* Revert r342942 "[MachineCopyPropagation] Reimplement CopyTracker in terms of ↵Hans Wennborg2018-09-271-58/+54
| | | | | | | | | | | | | | | | register units" It seems to have broken several targets, see comments on the llvm-commits thread. > Change the copy tracker to keep a single map of register units instead > of 3 maps of registers. This gives a very significant compile time > performance improvement to the pass. I measured a 30-40% decrease in > time spent in MCP on x86 and AArch64 and much more significant > improvements on out of tree targets with more registers. > > Differential Revision: https://reviews.llvm.org/D52374 llvm-svn: 343189
* [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlagOliver Stannard2018-09-274-3/+35
| | | | | | | | | | | These new instructions manipluate the NZCV bits, to convert between the regular Arm floating-point comare format and an alternative format. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52473 llvm-svn: 343187
* [mips] Add support MIPS r6 Debian triplesSimon Atanasyan2018-09-272-15/+31
| | | | | | | | | | | | | | | | | | | Debian uses different triples for MIPS r6 and paths. Here we use SubArch to determine whether it is r6, if we found `r6' in CPU section of triple. These new triples include: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D50857 llvm-svn: 343185
* [ORC] Use ExecutionSession's pre-constructed main JITDylib in LLJIT.Lang Hames2018-09-271-2/+2
| | | | | | | As of r342086 ExecutionSession automatically creates a 'main' JITDylib, so there is no need for LLJIT to create its own. llvm-svn: 343167
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-2789-267/+232
| | | | | | | | | | | | Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
* [WebAssembly] Fix MRI.hasOneNonDBGUse assert in WebAssemblyRegStackify pass Yury Delendik2018-09-261-2/+2
| | | | | | | | | | | | | | | | | Summary: The OneUseDominatesOtherUses in the WebAssemblyRegStackify not properly validates register use using hasOneUse. Since we added/modified DBG_VALUE the assert started catching valid cases. See also https://reviews.llvm.org/D49034#1247200 Fix verified by running the wasm waterfall. Reviewed By: dschuff Tags: #debug-info Differential Revision: https://reviews.llvm.org/D49034 llvm-svn: 343154
* [LoopInterchange] Preserve LCSSA.Florian Hahn2018-09-261-18/+54
| | | | | | | | | | | | | | | | | | This patch extends LoopInterchange to move LCSSA to the right place after interchanging. This is required for LoopInterchange to become a function pass. An alternative to the manual moving of the PHIs, we could also re-form the LCSSA phis for a set of interchanged loops, but that's more expensive. Reviewers: efriedma, mcrosier, davide Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D52154 llvm-svn: 343132
* AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patternsTom Stellard2018-09-261-1/+1
| | | | | | | | | | | | | | | | | | Summary: This is essentially NFC, because the complex pattern used for these patterns will fail on non-CI, but this makes the pattern consistent with other CI smrd patterns. It is also a performance improvement, because the pattern will now fail earlier on non-CI. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52469 llvm-svn: 343125
* Reapply r343058 with a fix for -DLLVM_ENABLE_THREADS=OFF.Lang Hames2018-09-261-9/+84
| | | | | | | | | Modifies lit to add a 'thread_support' feature that can be used in lit test REQUIRES clauses. The thread_support flag is set if -DLLVM_ENABLE_THREADS=ON and unset if -DLLVM_ENABLE_THREADS=OFF. The lit flag is used to disable the multiple-compile-threads-basic.ll testcase when threading is disabled. llvm-svn: 343122
* [DAG] SelectionDAGLegalize::ExpandLegalINT_TO_FP - use getFPExtendOrRound ↵Simon Pilgrim2018-09-261-11/+1
| | | | | | | | helper. NFCI. Handles SrcVT == DstVT as well. llvm-svn: 343121
* [AArch64] Extend single-operand FP insns to match Arm ARM (NFCI)Oliver Stannard2018-09-261-6/+7
| | | | | | | | | | | | | | | | | | The Armv8.3-A reference manual defines floating-point data-processing instructions with one source operand to have an opcode of 6 bits [20:15]. The current class in tablegen, BaseSingleOperandFPData, only allows [18:15]. This was ok because [20:19] could only be '00', with other encodings unallocated. Armv8.5-A brings in the FRINT group of instructions which use other values for these bits. This patch refactors the existing class a bit to allow using the full 6 bits of the opcode, as defined in the Arm ARM. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52474 llvm-svn: 343120
* Revert r343112 as CallFrameString API change has broken lldb buildsLuke Cheeseman2018-09-2614-82/+10
| | | | llvm-svn: 343114
* [AArch64] Refactor instructions that write PSTATE (NFCI)Oliver Stannard2018-09-261-9/+15
| | | | | | | | | | | Reuse some code in preparation for the v8.5A XAFlag/AXFlag instructions, which shares part of the encoding of the MSR-immediate. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52472 llvm-svn: 343113
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-09-2614-10/+82
| | | | | | - Reapply r343089 with a fix for DebugInfo/Sparc/gnu-window-save.ll llvm-svn: 343112
* [AArch64][AsmParser] Show name of missing feature for system instructionsOliver Stannard2018-09-261-24/+35
| | | | | | | | | | | | | | | | | Parsing of the system instructions (IC, DC, AT and TLBI) uses this function to show the required architecture when the operand is valid, but the architecture is not enabled. Armv8.5A adds a few different system instructions as part of optional features, so we need to extend it to show individual features, not just base architectures. This is NFC for now, but will be used by three different features added in v8.5A, and will be tested by them. Patch by David Spickett! Differential revision: https://reviews.llvm.org/D52478 llvm-svn: 343109
* [CodeGen] Always print register ties in MI::dump()Francis Visoiu Mistrih2018-09-261-1/+1
| | | | | | | | | It was the case when calling MO::dump(), but MI::dump() was still depending on hasComplexRegisterTies(). The MIR output is not affected. llvm-svn: 343107
* [PassTiming] cleaning up legacy PassTimingInfo interface. NFCI.Fedor Sergeev2018-09-263-51/+62
| | | | | | | | | | | | | | | | | | | | During D51276 discussion it was decided that legacy PassTimingInfo interface can not be reused for new pass manager's implementation of -time-passes. This is a cleanup in preparation for D51276 to make legacy interface as concise as possible, moving the PassTimingInfo from the header into the anonymous legacy namespace in .cpp. It is rather close to a revert of rL340872 in a sense that it hides the interface and gets rid of templates. However as compared to a complete revert it resides in a different translation unit and has an additional pass-instance counting funcitonality (PassIDCountMap). Reviewers: philip.pfaffe Differential Revision: https://reviews.llvm.org/D52356 llvm-svn: 343104
* Revert r343089 "[AArch64] - Return address signing dwarf support"Hans Wennborg2018-09-2614-82/+10
| | | | | | | | | | | | | | | | | | | This caused the DebugInfo/Sparc/gnu-window-save.ll test to fail. > Functions that have signed return addresses need additional dwarf support: > - After signing the LR, and before authenticating it, the LR register is in a > state the is unusable by a debugger or unwinder > - To account for this a new directive, .cfi_negate_ra_state, is added > - This directive says the signed state of the LR register has now changed, > i.e. unsigned -> signed or signed -> unsigned > - This directive has the same CFA code as the SPARC directive GNU_window_save > (0x2d), adding a macro to account for multiply defined codes > - This patch matches the gcc implementation of this support: > https://patchwork.ozlabs.org/patch/800271/ > > Differential Revision: https://reviews.llvm.org/D50136 llvm-svn: 343103
* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-2610-0/+40
| | | | | | | | | | | | | This patch allows targeting Armv8.5-A, adding the architecture to tablegen and setting the options to be identical to Armv8.4-A for the time being. Subsequent patches will add support for the different features included in the Armv8.5-A Reference Manual. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52470 llvm-svn: 343102
* [DAG] ExpandLegalINT_TO_FP - pull out repeated getValueType() call. NFCI.Simon Pilgrim2018-09-261-9/+9
| | | | llvm-svn: 343101
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