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* Metadata for annotating loops as parallel. The first consumer for this Pekka Jaaskelainen2013-02-132-0/+58
| | | | | | | | metadata is the loop vectorizer. See the documentation update for more info. llvm-svn: 175060
* Add registration for PPC-specific passes to allow the IR to be dumpedKrzysztof Parzyszek2013-02-133-3/+41
| | | | | | via -print-after-all. llvm-svn: 175058
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-131-0/+8
| | | | | | | | | | | This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. llvm-svn: 175057
* Use array_pod_sort.Bill Wendling2013-02-131-1/+1
| | | | llvm-svn: 175048
* Add some accessor and query methods for retrieving Attribute objects and such.Bill Wendling2013-02-132-0/+45
| | | | llvm-svn: 175046
* Make jumptables work for -staticReed Kotler2013-02-131-0/+2
| | | | llvm-svn: 175044
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky2013-02-131-0/+10
| | | | | | since a caller uses preserved registers across the call. llvm-svn: 175043
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-1/+1
| | | | | | assembly. llvm-svn: 175036
* [tsan] disable load widening in ThreadSanitizer modeKostya Serebryany2013-02-131-0/+6
| | | | llvm-svn: 175034
* [asan] fix confusing indentationKostya Serebryany2013-02-131-1/+2
| | | | llvm-svn: 175033
* Fix comment.Eric Christopher2013-02-131-2/+2
| | | | llvm-svn: 175024
* Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.Manman Ren2013-02-133-14/+16
| | | | | | | | | | | | | | RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs without emitting them at the end. We fix this by removing LDV from RegisterCoalescer. Also add an assertion to make sure we call emitDebugValues if DBG_VALUEs are removed at runOnMachineFunction. rdar://problem/13183203 Reviewed by Andy & Jakob llvm-svn: 175023
* [ms-inline-asm] Make sure the AsmRewrite list is sorted in lexical order.Chad Rosier2013-02-131-0/+5
| | | | | | rdar://13202662 llvm-svn: 175021
* Test commit. Fixed typo.David Peixotto2013-02-131-1/+1
| | | | llvm-svn: 175020
* Fix commentArnaud A. de Grandmaison2013-02-131-2/+2
| | | | | | visitSExt is an adapted copy of the related visitZExt method, so adapt the comment accordingly. llvm-svn: 175019
* Changed isStoredObjCPointer => IsStoredObjCPointer. No functionality change.Michael Gottesman2013-02-121-4/+4
| | | | llvm-svn: 175017
* Actually delete this code, since it's really not clear what it'sDan Gohman2013-02-121-24/+0
| | | | | | trying to do. llvm-svn: 175014
* [ms-inline-asm] Implement align directive (which is roughly equivalent to ↵Chad Rosier2013-02-121-9/+43
| | | | | | | | | | .align). Also, allow _EMIT and __EMIT for the emit directive. We already do the same for TYPE, SIZE, and LENGTH. rdar://13200215 llvm-svn: 175008
* This patch just fixes up various llvm formattingJack Carter2013-02-122-3/+4
| | | | | | | | | | violations such as tabs, blanks at eol and long lines. llvm-svn: 175007
* Add static cast to unsigned char whenever a character classification ↵Guy Benyei2013-02-1215-53/+77
| | | | | | function is called with a signed char argument, in order to avoid assertions in Windows Debug configuration. llvm-svn: 175006
* Record PRE predecessors with a SmallVector instead of a DenseMap, andDan Gohman2013-02-121-8/+9
| | | | | | avoid a second pred_iterator traversal. llvm-svn: 175001
* [ms-inline asm] Pass the length of the IDVal, so we can do a proper AsmRewrite.Chad Rosier2013-02-121-4/+5
| | | | llvm-svn: 174999
* [ms-inline asm] Accept the emit directive as either _emit or __emit.Chad Rosier2013-02-121-2/+2
| | | | llvm-svn: 174998
* When disabling PRE for a value is directly redundant with itselfDan Gohman2013-02-121-0/+2
| | | | | | | (through a loop), don't continue to iterate through the reamining predecessors. llvm-svn: 174994
* Check that pointers are removed from maps before calling delete on the pointers,Dan Gohman2013-02-121-3/+3
| | | | | | for tidiness' sake. llvm-svn: 174988
* Minor code simplification.Dan Gohman2013-02-121-1/+1
| | | | llvm-svn: 174985
* [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier2013-02-121-19/+40
| | | | | | | | | | | | | | This is complicated by backward labels (e.g., 0b can be both a backward label and a binary zero). The current implementation assumes [0-9]b is always a label and thus it's possible for 0b and 1b to not be interpreted correctly for ms-style inline assembly. However, this is relatively simple to fix in the inline assembly (i.e., drop the [bB]). This patch also limits backward labels to [0-9]b, so that only 0b and 1b are ambiguous. Part of rdar://12470373 llvm-svn: 174983
* Allow optionally generating pubnames section in DWARF info. IntroduceKrzysztof Parzyszek2013-02-125-2/+95
| | | | | | option "generate-dwarf-pubnames" to control it, set to "false" by default. llvm-svn: 174981
* Equal treatment of labels and other terminators in MI DAG construction.Sergei Larin2013-02-121-1/+1
| | | | | | | MI sched DAG construction allows targets to include terminators into scheduling DAG. Extend this functionality to labels as well. llvm-svn: 174977
* Add support for the pubnames section to llvm-dwarfdump.Krzysztof Parzyszek2013-02-122-0/+23
| | | | llvm-svn: 174976
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-20/+123
| | | | | | instructions. llvm-svn: 174973
* PR14562 - Truncation of left shift became undefPaul Redmond2013-02-121-2/+9
| | | | | | | | | | | DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem llvm-svn: 174972
* [NVPTX] Disable vector registersJustin Holewinski2013-02-1217-1997/+1274
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. llvm-svn: 174968
* [ASan] Do not use kDefaultShort64bitShadowOffset on Mac, where the binaries ↵Alexander Potapenko2013-02-121-1/+2
| | | | | | may get mapped at 0x100000000+ and thus may interleave with the shadow. llvm-svn: 174964
* R600: Fix regression with shadow array sampler on pre-SI GPUs.Michel Danzer2013-02-121-1/+1
| | | | | | | | | | | | | | | 'R600/SI: Use proper instructions for array/shadow samplers.' removed two cases from TEX_SHADOW. Vincent Lejeune reported on IRC that this broke some shadow array piglit tests with the r600g driver. Reinstating the removed cases should fix this, and still works with radeonsi as well. I will follow up with some lit tests which would have caught the regression. NOTE: This is a candidate for the Mesa stable branch. Tested-by: Vincent Lejeune <vljn@ovi.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174963
* [asan] change the default mapping offset on x86_64 to 0x7fff8000. This gives ↵Kostya Serebryany2013-02-121-3/+5
| | | | | | roughly 5% speedup. Since this is an ABI change, bump the asan ABI version by renaming __asan_init to __asan_init_v1. llvm part, compiler-rt part will follow llvm-svn: 174957
* Merge the collected attributes into the call instruction's attributes.Bill Wendling2013-02-121-2/+2
| | | | llvm-svn: 174955
* Have the bitcode writer and reader handle the new attribute references.Bill Wendling2013-02-122-33/+11
| | | | | | | | The bitcode writer emits a reference to the attribute group that the object at the given index refers to. The bitcode reader is modified to read this in and map it back to the attribute group. llvm-svn: 174952
* Use the AttributeSet as the 'key' to the map instead of the 'raw' pointer.Bill Wendling2013-02-122-5/+6
| | | | llvm-svn: 174950
* Support string attributes in the AttrBuilder.Bill Wendling2013-02-121-11/+25
| | | | llvm-svn: 174948
* Don't consider definitions by other PHIs live-in when trimming a PHI source'sCameron Zwarich2013-02-121-1/+5
| | | | | | live range after inserting a copy at the end of a block. llvm-svn: 174945
* Fix indentation.Cameron Zwarich2013-02-121-2/+2
| | | | llvm-svn: 174944
* Add a hidden option to PHIElimination to split all critical edges. This isCameron Zwarich2013-02-121-4/+9
| | | | | | | particularly useful for catching issues with architectures that have exotic terminators like MIPS. llvm-svn: 174938
* Add blocks to the LiveIntervalAnalysis RegMaskBlocks array when splittingCameron Zwarich2013-02-121-2/+6
| | | | | | a critical edge. llvm-svn: 174936
* Fix the updating of LiveIntervals after splitting a critical edge. PHI operandCameron Zwarich2013-02-121-12/+3
| | | | | | | live ranges should always be extended, and the only successor that should be considered for extension of other ranges is the target of the split edge. llvm-svn: 174935
* Check type for legality before forming a select from loads.Pete Cooper2013-02-121-1/+3
| | | | | | | | Sorry for the lack of a test case. I tried writing one for i386 as i know selects are illegal on this target, but they are actually considered legal by isel and expanded later. I can't see any targets to trigger this, but checking for the legality of a node before forming it is general goodness. llvm-svn: 174934
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-121-0/+33
| | | | | | | | | A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 llvm-svn: 174933
* Cost model: Add check for reverse shuffles to CostModel analysisArnold Schwaighofer2013-02-121-0/+18
| | | | | | | | | | Check for reverse shuffles in the CostModel analysis pass and query TargetTransform info accordingly. This allows us we can write test cases for reverse shuffles. radar://13171406 llvm-svn: 174932
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-1/+37
| | | | | | | | | | | | | | | Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 llvm-svn: 174929
* Update error message due to previous commit, r174926.Chad Rosier2013-02-121-1/+3
| | | | llvm-svn: 174927
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