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* [ASAN] Add doFinalization to reset stateKeno Fischer2015-12-051-0/+11
| | | | | | | | | | | | | | | Summary: If the same pass manager is used for multiple modules ASAN complains about GlobalsMD being initialized twice. Fix this by resetting GlobalsMD in a new doFinalization method to allow this use case. Reviewers: kcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14962 llvm-svn: 254851
* [X86][ADX] Added memory folding patterns and stack folding testsSimon Pilgrim2015-12-051-0/+6
| | | | llvm-svn: 254844
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-0518-80/+82
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* [X86][FMA4] Explicitly set the domain of FMA4 float/double scalar instructionsSimon Pilgrim2015-12-051-29/+32
| | | | | | Both were defaulting to the float domain - now matches the packed instructions. llvm-svn: 254841
* [PGO] Add version to getPGOFuncName methodXinliang David Li2015-12-051-3/+5
| | | | | | | | | Different version of indexed format may use different name uniquing schemes for static functions. Pass the version info to the name interface so that different schmes can be picked (for profile lookup). llvm-svn: 254838
* Normalize successors' probabilities when building MBBs for jump table.Cong Hou2015-12-051-0/+2
| | | | llvm-svn: 254837
* [llvm-dwp] Support debug_tu_indexDavid Blaikie2015-12-051-0/+10
| | | | llvm-svn: 254827
* [WebAssembly] Implement ReverseBranchCondition, and re-enable ↵Dan Gohman2015-12-057-17/+178
| | | | | | | | | | | | | MachineBlockPlacement This patch introduces a codegen-only instruction currently named br_unless, which makes it convenient to implement ReverseBranchCondition and re-enable the MachineBlockPlacement pass. Then in a late pass, it lowers br_unless back into br_if. Differential Revision: http://reviews.llvm.org/D14995 llvm-svn: 254826
* [libFuzzer] don't reload the corpus more than once every secondKostya Serebryany2015-12-051-1/+6
| | | | llvm-svn: 254824
* Fix a typo in LoopVectorize.cpp. NFC.Cong Hou2015-12-051-1/+1
| | | | llvm-svn: 254813
* [WebAssembly] Fix scheduling dependencies in register-stackified codeDan Gohman2015-12-051-9/+42
| | | | | | | | | | | Add physical register defs to instructions used from stackified instructions to prevent them from being scheduled into the middle of a stack sequence. This is a conservative measure which may be loosened in the future. Differential Revision: http://reviews.llvm.org/D15252 llvm-svn: 254811
* [WebAssembly] Support constant offsets on loads and storesDerek Schuff2015-12-052-75/+86
| | | | | | | | | This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
* [EarlyCSE] IsSimple vs IsVolatile naming clarification (NFC)Philip Reames2015-12-052-13/+13
| | | | | | | | | | | | When the notion of target specific memory intrinsics was introduced to EarlyCSE, the commit confused the notions of volatile and simple memory access. Since I'm about to start working on this area, cleanup the naming so that patches aren't horribly confusing. Note that the actual implementation was always bailing if the load or store wasn't simple. Reminder: - "volatile" - C++ volatile, can't remove any memory operations, but in principal unordered - "ordered" - imposes ordering constraints on other nearby memory operations - "atomic" - can't be split or sheared. In LLVM terms, all "ordered" operations are also atomic so the predicate "isAtomic" is often used. - "simple" - a load which is none of the above. These are normal loads and what most of the optimizer works with. llvm-svn: 254805
* [PassManager] Ensure destructors of cached AnalysisUsage objects are runPhilip Reames2015-12-041-1/+1
| | | | | | In 254760, I introduced the usage of a BumpPtrAllocator for the AnalysisUsage instances held by the PassManger. This turns out to have been incorrect since a BumpPtrAllocator does not run the destructors of objects when deallocating memory. Since a few of our SmallVector's had grown beyond their small size, we end up with some leaked memory. We need to use a SpecificBumpPtrAllocator instead. llvm-svn: 254803
* [ThinLTO] Helper for performing renaming/promotion on a moduleTeresa Johnson2015-12-041-0/+12
| | | | | | | | | Creates a module and performs necessary renaming/promotion of locals that may be exported to another module. Split out of D15024. llvm-svn: 254802
* Add FeatureLAHFSAHF to amdfam10 as well.Hans Wennborg2015-12-041-1/+1
| | | | llvm-svn: 254801
* [WebAssembly] Initial varargs support.Dan Gohman2015-12-047-18/+108
| | | | | | | | | Full varargs support will depend on prologue/epilogue support, but this patch gets us started with most of the basic infrastructure. Differential Revision: http://reviews.llvm.org/D15231 llvm-svn: 254799
* X86: Don't emit SAHF/LAHF for 64-bit targets unless explicitly supportedHans Wennborg2015-12-046-25/+86
| | | | | | | | | | | | | | | These instructions are not supported by all CPUs in 64-bit mode. Emitting them causes Chromium to crash on start-up for users with such chips. (GCC puts these instructions behind -msahf on 64-bit for the same reason.) This patch adds FeatureLAHFSAHF, enables it by default for 32-bit targets and modern CPUs, and changes X86InstrInfo::copyPhysReg back to the lowering from before r244503 when the instructions are not available. Differential Revision: http://reviews.llvm.org/D15240 llvm-svn: 254793
* [libFuzzer] compute base64 in-process instead of using an external lib. ↵Kostya Serebryany2015-12-045-10/+45
| | | | | | Since libFuzzer should not depend on anything, just re-implement base64 encoder. PR25746 llvm-svn: 254784
* MSVC complains about this being ambiguous.Rafael Espindola2015-12-041-2/+2
| | | | llvm-svn: 254782
* Always pass a diagnostic handler to the linker.Rafael Espindola2015-12-042-14/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Before this patch the diagnostic handler was optional. If it was not passed, the one in the LLVMContext was used. That is probably not a pattern we want to follow. If each area has an optional callback, there is a sea of callbacks and it is hard to follow which one is called. Doing this also found cases where the callback is a nice addition, like testing that no errors or warnings are reported. The other option is to always use the diagnostic handler in the LLVMContext. That has a few problems * To implement the C API we would have to set the diag handler and then set it back to the original value. * Code that creates the context might be far away from code that wants the diagnostics. I do have a patch that implements the second option and will send that as an RFC. llvm-svn: 254777
* [SimplifyLibCalls] Optimization for pow(x, n) where n is some constantWeiming Zhao2015-12-041-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In order to avoid calling pow function we generate repeated fmul when n is a positive or negative whole number. For each exponent we pre-compute Addition Chains in order to minimize the no. of fmuls. Refer: http://wwwhomes.uni-bielefeld.de/achim/addition_chain.html We pre-compute addition chains for exponents upto 32 (which results in a max of 7 fmuls). For eg: 4 = 2+2 5 = 2+3 6 = 3+3 and so on Hence, pow(x, 4.0) ==> y = fmul x, x x = fmul y, y ret x For negative exponents, we simply compute the reciprocal of the final result. Note: This transformation is only enabled under fast-math. Patch by Mandeep Singh Grang <mgrang@codeaurora.org> Reviewers: weimingz, majnemer, escha, davide, scanon, joerg Subscribers: probinson, escha, llvm-commits Differential Revision: http://reviews.llvm.org/D13994 llvm-svn: 254776
* [AArch64] Expand vector SDIVREM/UDIVREM operations.Chad Rosier2015-12-041-0/+4
| | | | | | | http://reviews.llvm.org/D15214 Patch by Ana Pazos <apazos@codeaurora.org>! llvm-svn: 254773
* [OperandBundles] Allow operand-specific attributes in operand bundlesSanjoy Das2015-12-041-2/+2
| | | | | | | | | | | | | Currently `OperandBundleUse::operandsHaveAttr` computes its result without being given a specific operand. This is problematic because it forces us to say that, e.g., even non-pointer operands in `"deopt"` operand bundles are `readonly`, which doesn't make sense. This commit changes `operandsHaveAttr` to work in the context of a specific operand, so that we can give the operand attributes that make sense for the operands's `llvm::Type`. llvm-svn: 254764
* [LegacyPassManager] Reduce memory usage for AnalysisUsagePhilip Reames2015-12-041-8/+24
| | | | | | | | | | The LegacyPassManager was storing an instance of AnalysisUsage for each instance of each pass. In practice, most instances of a single pass class share the same dependencies. We can't rely on this because passes can (and some do) have dynamic dependencies based on instance options. We can exploit the likely commonality by uniqueing the usage information after querying the pass, but before storing it into the pass manager. This greatly reduces memory consumption by the AnalysisUsage objects. For a long pass pipeline, I measured a decrease in memory consumption for this storage of about 50%. I have not measured on the default O3 pipeline, but I suspect it will see some benefit as well since many passes are repeated (e.g. InstCombine). Differential Revision: http://reviews.llvm.org/D14677 llvm-svn: 254760
* ScheduleDAGInstrs: Move LiveIntervals field to ScheduleDAGMIMatthias Braun2015-12-041-2/+1
| | | | | | | Now that ScheduleDAGInstrs doesn't need it anymore we can move the field down the class hierarcy to ScheduleDAGMI. llvm-svn: 254759
* [WebAssembly] Add several more calling conventions to the supported list.Dan Gohman2015-12-041-2/+7
| | | | llvm-svn: 254741
* fix formatting; NFCSanjay Patel2015-12-041-25/+18
| | | | llvm-svn: 254739
* [CXX TLS calling convention] Add CXX TLS calling convention.Manman Ren2015-12-045-0/+13
| | | | | | | | | | | | | | | | | | | | | This commit adds a new target-independent calling convention for C++ TLS access functions. It aims to minimize overhead in the caller by perserving as many registers as possible. The target-specific implementation for X86-64 is defined as following: Arguments are passed as for the default C calling convention The same applies for the return value(s) The callee preserves all GPRs - except RAX and RDI The access function makes C-style TLS function calls in the entry and exit block, C-style TLS functions save a lot more registers than normal calls. The added calling convention ties into the existing implementation of the C-style TLS functions, so we can't simply use existing calling conventions such as preserve_mostcc. rdar://9001553 llvm-svn: 254737
* [llvm-dwp] Retrieve the DWOID from the CU for the cu_index entryDavid Blaikie2015-12-041-2/+8
| | | | llvm-svn: 254731
* [WebAssembly] Give names to the callseq begin and end instructions.Dan Gohman2015-12-041-4/+4
| | | | llvm-svn: 254730
* [WebAssembly] clang-format CallingConvSupported. NFC.Dan Gohman2015-12-041-4/+2
| | | | llvm-svn: 254729
* [WebAssembly] Factor out the list of supported calling conventions.Dan Gohman2015-12-041-4/+13
| | | | llvm-svn: 254728
* [WebAssembly] Check for more unsupported ABI flags.Dan Gohman2015-12-041-1/+26
| | | | llvm-svn: 254727
* [WebAssembly] Use SelectionDAG::getUNDEF. NFC.Dan Gohman2015-12-041-1/+1
| | | | llvm-svn: 254726
* [Hexagon] Simplify LowerCONCAT_VECTORS, handle different types betterKrzysztof Parzyszek2015-12-041-58/+55
| | | | llvm-svn: 254724
* Modernize the C++ APIs for creating LTO modules.Rafael Espindola2015-12-041-73/+58
| | | | | | | | | | | | | | | | This is a continuation of r253367. These functions return is owned by the caller, so they return std::unique_ptr now. The call can fail, so the return is wrapped in ErrorOr. They have a context where to report diagnostics, so they don't need to take a string out parameter. With this there are no call to getGlobalContext in lib/LTO. llvm-svn: 254721
* [Hexagon] Using multiply instead of shift on signed number which can be UBColin LeMahieu2015-12-041-2/+2
| | | | llvm-svn: 254719
* [SystemZ] Bugfix: Don't add CC twice to new three-address instruction.Jonas Paulsson2015-12-041-4/+10
| | | | | | | | | | | Since BuildMI() automatically adds the implicit operands for a new instruction, adding the old instructions CC operand resulted in that there were two CC imp-def operands, where only one was marked as dead. This caused buildSchedGraph() to miss dependencies on the CC reg. Review by Ulrich Weigand llvm-svn: 254714
* LEA code size optimization pass (Part 1): Remove redundant address ↵Alexey Bataev2015-12-044-0/+332
| | | | | | | | | recalculations, by Andrey Turetsky Add new x86 pass which replaces address calculations in load or store instructions with def register of existing LEA (must be in the same basic block), if the LEA calculates address that differs only by a displacement. Works only with -Os or -Oz. Differential Revision: http://reviews.llvm.org/D13294 llvm-svn: 254712
* [asan] Fix dynamic allocas unpoisoning on PowerPC64.Yury Gribov2015-12-041-2/+17
| | | | | | | | | | | | | | | For PowerPC64 we cannot just pass SP extracted from @llvm.stackrestore to _asan_allocas_unpoison due to specific ABI requirements (http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html#DYNAM-STACK). This patch adds the value returned by @llvm.get.dynamic.area.offset to extracted from @llvm.stackrestore stack pointer, so dynamic allocas unpoisoning stuff would work correctly on PowerPC64. Patch by Max Ostapenko. Differential Revision: http://reviews.llvm.org/D15108 llvm-svn: 254707
* Revert "[BranchFolding] Merge MMOs during tail merge"Rafael Espindola2015-12-041-26/+16
| | | | | | | | This reverts commit r254694. It broke bootstrap. llvm-svn: 254700
* Move a call to getGlobalContext out of lib/LTO.Rafael Espindola2015-12-041-9/+2
| | | | llvm-svn: 254696
* [BranchFolding] Merge MMOs during tail mergeJunmo Park2015-12-041-16/+26
| | | | | | | | | | | | | | | | | Summary: If we remove the MMOs from Load/Store instructions, they are treated as volatile. This makes other optimization passes unhappy. eg. Load/Store Optimization So, it looks better to merge, not remove. Reviewers: gberry, mcrosier Subscribers: gberry, llvm-commits Differential Revision: http://reviews.llvm.org/D14797 llvm-svn: 254694
* [Orc] Rename JITCompileCallbackManagerBase to JITCompileCallbackManager.Lang Hames2015-12-043-3/+3
| | | | | | | | | This class is turning into a useful interface, rather than an implementation detail, so I'm dropping the 'Base' suffix. No functional change. llvm-svn: 254693
* IR: Use format_hex instead of handrolling the conversion. NFCJustin Bogner2015-12-041-47/+17
| | | | | | Cleans up some very old code in AsmWriter's WriteConstantInternal. llvm-svn: 254688
* Revert "[llvm-profdata] Add support for weighted merge of profile data"Nathan Slingerland2015-12-041-12/+2
| | | | | | | | This reverts commit b7250858d96b8ce567681214273ac0e62713c661. Reverting in order to investigate Windows test failure. llvm-svn: 254687
* (no commit message)Junmo Park2015-12-041-1/+1
| | | | llvm-svn: 254686
* [ARM] When a bitcast is about to be turned into a VMOVDRR, try to combine itQuentin Colombet2015-12-041-0/+55
| | | | | | | | | | | with its source instead of forcing the values on GPRs. This improves the lowering of vector code when such bitcasts happen in the middle of vector computations. rdar://problem/23691584 llvm-svn: 254684
* ScheduleDAGInstrs: Rework schedule graph builder.Matthias Braun2015-12-041-66/+161
| | | | | | | | | | | | | | | | | | Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254683
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