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* Remove a temporary variable and just construct a unique_ptr directly using ↵Craig Topper2014-09-121-9/+6
| | | | | | make_unique. llvm-svn: 217655
* [MCJIT] Improve the "stub not found" diagnostic in RuntimeDyldChecker.Lang Hames2014-09-111-1/+4
| | | | | | | | | | | | | A "stub found found" diagnostic is emitted when RuntimeDyldChecker's stub lookup logic fails to find the requested stub. The obvious reason for the failure is that no such stub has been created, but it can also fail for internal symbols if the symbol offset is not computed correctly (E.g. due to a mangled relocation addend). This patch adds a comment about the latter case so that it's not overlooked. Inspired by confusion experienced during test case construction for r217635. llvm-svn: 217643
* R600/SI: Fix off by 1 error in used register countMatt Arsenault2014-09-111-2/+4
| | | | | | | The register numbers start at 0, so if only 1 register was used, this was reported as 0. llvm-svn: 217636
* Support: Use llvm::COFF::BigObjMagicRui Ueyama2014-09-111-7/+15
| | | | | | | Use llvm::COFF::BigObjMagic insetad of the string literal. Also checks the version number. llvm-svn: 217633
* Support: Delete {aligned_,}{u,}{little,big}8_tRui Ueyama2014-09-111-1/+0
| | | | | | | The byte has no endianness, so these types don't make sense. uint8_t should be used instead. llvm-svn: 217631
* [C API] Make the 'lower switch' pass available via the C API.Juergen Ributzka2014-09-111-0/+4
| | | | llvm-svn: 217630
* [CodeGenPrepare] Teach the addressing mode matcher how to promote zext.Quentin Colombet2014-09-111-13/+56
| | | | | | I.e., teach it about 'sext (zext a to ty) to ty2' => zext a to ty2. llvm-svn: 217629
* Remove the unused string section symbol parameter from DwarfFile::emitStringsDavid Blaikie2014-09-119-61/+43
| | | | | | | | | | | | | | | | | | | And since it /looked/ like the DwarfStrSectionSym was unused, I tried removing it - but then it turned out that DwarfStringPool was reconstructing the same label (and expecting it to have already been emitted) and uses that. So I kept it around, but wanted to pass it in to users - since it seemed a bit silly for DwarfStringPool to have it passed in and returned but itself have no use for it. The only two users don't handle strings in both .dwo and .o files so they only ever need the one symbol - no need to keep it (and have an unused symbol) in the DwarfStringPool used for fission/.dwo. Refactor a bunch of accelerator table usage to remove duplication so I didn't have to touch 4-5 callers. llvm-svn: 217628
* Support: improve identify_magic to recognize COFF bigobjRui Ueyama2014-09-111-3/+9
| | | | | | | identify_magic recognized a COFF bigobj as an import library file. This patch fixes that. llvm-svn: 217627
* Misc cleanups to the FileSytem api.Rafael Espindola2014-09-114-66/+43
| | | | | | | | | | | | | | | | The main difference is the removal of std::error_code exists(const Twine &path, bool &result); It was an horribly redundant interface since a file not existing is also a valid error_code. Now we have an access function that returns just an error_code. This is the only function that has to be implemented for Unix and Windows. The functions can_write, exists and can_execute an now just wrappers. One still has to be very careful using these function to avoid introducing race conditions (Time of check to time of use). llvm-svn: 217625
* [PATCH, PowerPC] Accept 'U' and 'X' constraints in inline asmBill Schmidt2014-09-111-0/+10
| | | | | | | | | | | | | | | | | | Inline asm may specify 'U' and 'X' constraints to print a 'u' for an update-form memory reference, or an 'x' for an indexed-form memory reference. However, these are really only useful in GCC internal code generation. In inline asm the operand of the memory constraint is typically just a register containing the address, so 'U' and 'X' make no sense. This patch quietly accepts 'U' and 'X' in inline asm patterns, but otherwise does nothing. If we ever unexpectedly see a non-register, we'll assert and sort it out afterwards. I've added a new test for these constraints; the test case should be used for other asm-constraints changes down the road. llvm-svn: 217622
* [MCJIT] Add support for ARM HALF_DIFF relocations to MCJIT.Lang Hames2014-09-114-58/+183
| | | | | | Fixes <rdar://problem/18297804>. llvm-svn: 217620
* Provide an implementation of getNoopForMachoTarget for SPARC.Brad Smith2014-09-112-0/+7
| | | | llvm-svn: 217611
* Add DAG combine for shl + add of constants.Matt Arsenault2014-09-111-32/+12
| | | | | | | | | | | | | | Do (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) This is already done for multiplies, but since multiplies by powers of two are turned into shifts, we also need to handle it here. This might want checks for isLegalAddImmediate to avoid transforming an add of a legal immediate with one that isn't. llvm-svn: 217610
* [MCJIT] Take the relocation addend into account when applying ARM MachO VANILLALang Hames2014-09-111-1/+2
| | | | | | | | and BR24 relocations. <rdar://problem/18296496> llvm-svn: 217605
* [AVX512] Fix miscompile for unpackAdam Nemet2014-09-111-56/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r189189 implemented AVX512 unpack by essentially performing a 256-bit unpack between the low and the high 256 bits of src1 into the low part of the destination and another unpack of the low and high 256 bits of src2 into the high part of the destination. I don't think that's how unpack works. AVX512 unpack simply has more 128-bit lanes but other than it works the same way as AVX. So in each 128-bit lane, we're always interleaving certain parts of both operands rather different parts of one of the operands. E.g. for this: __v16sf a = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; __v16sf b = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }; __v16sf c = __builtin_shufflevector(a, b, 0, 8, 1, 9, 4, 12, 5, 13, 16, 24, 17, 25, 20, 28, 21, 29); we generated punpcklps (notice how the elements of a and b are not interleaved in the shuffle). In turn, c was set to this: 0 16 1 17 4 20 5 21 8 24 9 25 12 28 13 29 Obviously this should have just returned the mask vector of the shuffle vector. I mostly reverted this change and made sure the original AVX code worked for 512-bit vectors as well. Also updated the tests because they matched the logic from the code. llvm-svn: 217602
* Move constant-sized bitvector to the stack.Benjamin Kramer2014-09-111-2/+2
| | | | llvm-svn: 217600
* Combine fmul vector FP constants when unsafe math is allowed.Sanjay Patel2014-09-111-6/+22
| | | | | | | | | | | | | | | | | | | This is an extension of the change made with r215820: http://llvm.org/viewvc/llvm-project?view=revision&revision=215820 That patch allowed combining of splatted vector FP constants that are multiplied. This patch allows combining non-uniform vector FP constants too by relaxing the check on the type of vector. Also, canonicalize a vector fmul in the same way that we already do for scalars - if only one operand of the fmul is a constant, make it operand 1. Otherwise, we miss potential folds. This fold is also done by -instcombine, but it's possible that extra fmuls may have been generated during lowering. Differential Revision: http://reviews.llvm.org/D5254 llvm-svn: 217599
* typoSanjay Patel2014-09-111-1/+1
| | | | llvm-svn: 217597
* R600: Add cmpxchg instruction for evergreenAaron Watry2014-09-112-5/+29
| | | | | | | | | | | | | | | | | Refactored the R600_LDS_1A2D class a bit to get it to actually work. It seemed to be previously unused and broken. We also have to disable the conversion to the noret variant for now in R600ISelLowering because the getLDSNoRetOp method only handles 1A1D LDS ops. Someone can feel free to modify the AMDGPU::getLDSNoRetOp method to work for more than 1A1D variants of LDS operations. It's being left as a future TODO for now. Signed-off-by: Aaron Watry <awatry at gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217596
* R600: Add LDS_WRXCHG[_RET] instructions for Evergreen.Aaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217594
* R600: Add LDS_MIN_[U]INT[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+8
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217593
* R600: Add LDS_XOR[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217592
* R600: Add LDS_OR[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217591
* R600: Add LDS_AND[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217590
* R600: Add LDS_MAX_[U]INT[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+8
| | | | | | | | | | | | | This was only present for SI before. Cayman may still be missing, but I am unable to test that currently. v2: Don't create atomicrmw max tests in separate file Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> CC: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 217589
* [AlignmentFromAssumptions] Don't crash just because the target is 32-bitHal Finkel2014-09-111-0/+4
| | | | | | | | | We used to crash processing any relevant @llvm.assume on a 32-bit target (because we'd ask SE to subtract expressions of differing types). I've copied our 'simple.ll' test, but with the data layout from arm-linux-gnueabihf to get some meaningful test coverage here. llvm-svn: 217574
* Build correct vector filled with undef nodesDavid Xu2014-09-111-4/+20
| | | | llvm-svn: 217570
* R600/SI: Fix losing chain when fixing reg class of loads.Matt Arsenault2014-09-101-6/+14
| | | | | | | The lost chain resulting in earlier side effecting nodes being deleted. llvm-svn: 217561
* R600/SI: Report offset in correct units for st64 DS instructionsMatt Arsenault2014-09-101-0/+15
| | | | | | | | | | | Need to convert the 64 element offset into bytes, not just the element size like the normal case instructions. Noticed by inspection. This can't be hit now because st64 instructions aren't emitted during instruction selection, and the post-RA scheduler isn't enabled. llvm-svn: 217560
* R600: Custom lower fremMatt Arsenault2014-09-102-0/+20
| | | | llvm-svn: 217553
* Add doInitialization/doFinalization to DataLayoutPass.Rafael Espindola2014-09-106-13/+16
| | | | | | | | | | | | | With this a DataLayoutPass can be reused for multiple modules. Once we have doInitialization/doFinalization, it doesn't seem necessary to pass a Module to the constructor. Overall this change seems in line with the idea of making DataLayout a required part of Module. With it the only way of having a DataLayout used is to add it to the Module. llvm-svn: 217548
* [AlignmentFromAssumptions] Don't divide by zero for unknown starting alignmentHal Finkel2014-09-101-2/+4
| | | | | | | | | | The routine that determines an alignment given some SCEV returns zero if the answer is unknown. In a case where we could determine the increment of an AddRec but not the starting alignment, we would compute the integer modulus by zero (which is illegal and traps). Prevent this by returning early if either the start or increment alignment is unknown (zero). llvm-svn: 217544
* [AArch64] Revert r216141 for cycloneGerolf Hoflehner2014-09-101-1/+1
| | | | | | | | | | The increase of the interleave factor to 4 has side-effects like performance losses eg. due to reminder loops being executed more frequently and may increase code size. It requires more analysis and careful heuristic tuning. Expect double digit gains in small benchmarks like lowercase.c and losses in puzzle.c. llvm-svn: 217540
* [PassManager] Adding Hidden attribute to EnableMLSM optionGerolf Hoflehner2014-09-101-2/+2
| | | | llvm-svn: 217539
* [MergedLoadStoreMotion] Move pass enabling option to PassManagerBuilderGerolf Hoflehner2014-09-102-7/+8
| | | | llvm-svn: 217538
* Cleanup: Use the appropriate API for accessing the DIVariable of aAdrian Prantl2014-09-101-1/+1
| | | | | | DBG_VALUE intrinsic. llvm-svn: 217533
* Make CallingConv::ID an alias of "unsigned".Alexey Samsonov2014-09-102-10/+6
| | | | | | | | | | | | | | | | | | | | Summary: Make CallingConv::ID a plain unsigned instead of enum with a fixed set of valus. LLVM IR allows arbitraty calling conventions (you are free to write cc12345), and loading them as enum is an undefined behavior. This was reported by UBSan. Test Plan: llvm regression test suite Reviewers: nicholas Reviewed By: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5248 llvm-svn: 217529
* Rename getMaximumUnrollFactor -> getMaxInterleaveFactor; also rename option ↵Sanjay Patel2014-09-108-53/+53
| | | | | | | | | | | names controlling this variable. "Unroll" is not the appropriate name for this variable. Clang already uses the term "interleave" in pragmas and metadata for this. Differential Revision: http://reviews.llvm.org/D5066 llvm-svn: 217528
* Removed misleading comment.Gerolf Hoflehner2014-09-101-1/+0
| | | | llvm-svn: 217527
* [AArch64] Address Chad's post commit review comments for r217504 (PBQP ↵Arnaud A. de Grandmaison2014-09-101-11/+10
| | | | | | experimental support) llvm-svn: 217518
* typoSanjay Patel2014-09-101-1/+1
| | | | llvm-svn: 217516
* Fix comments of createReplaceableForwardDecl() and createForwardDecl().Frederic Riss2014-09-101-4/+3
| | | | | | | | | | | | | Noticed while trying to understand how the merge of forward decalred types and defintions work. Reviewers: echristo, dblaikie, aprantl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5291 llvm-svn: 217514
* [AArch64] Pacify lld buildbot complaining about an unused static function in ↵Arnaud A. de Grandmaison2014-09-101-0/+2
| | | | | | release build. llvm-svn: 217505
* [AArch64] Add experimental PBQP supportArnaud A. de Grandmaison2014-09-105-2/+435
| | | | | | | | | | This adds target specific support for using the PBQP register allocator on the AArch64, for the A57 cpu. By default, the PBQP allocator is not used, unless explicitely required on the command line with "-aarch64-pbqp". llvm-svn: 217504
* [AArch 64] Use a constant pool load for weak symbol references whenAsiri Rathnayake2014-09-104-6/+39
| | | | | | | | | | | | | | using static relocation model and small code model. Summary: currently we generate GOT based relocations for weak symbol references regardless of the underlying relocation model. This should be change so that in static relocation model we use a constant pool load instead. Patch from: Keith Walker Reviewers: Renato Golin, Tim Northover llvm-svn: 217503
* Add missing HWEncoding to base register class.Sid Manning2014-09-101-8/+10
| | | | | | | This change gives tblgen the information needed to fill in the HexagonRegEncodingTable. llvm-svn: 217500
* Attempt to pacify buildbots.David Majnemer2014-09-101-11/+0
| | | | llvm-svn: 217499
* ARM: don't size-reduce STMs using the LR register.Tim Northover2014-09-101-1/+1
| | | | | | | | | The only Thumb-1 multi-store capable of using LR is the PUSH instruction, which translates to STMDB, so we shouldn't convert STMIAs. Patch by Sergey Dmitrouk. llvm-svn: 217498
* Object: Add support for bigobjDavid Majnemer2014-09-102-114/+161
| | | | | | | | | | | | | | | | | | | | | | This adds support for reading the "bigobj" variant of COFF produced by cl's /bigobj and mingw's -mbig-obj. The most significant difference that bigobj brings is more than 2**16 sections to COFF. bigobj brings a few interesting differences with it: - It doesn't have a Characteristics field in the file header. - It doesn't have a SizeOfOptionalHeader field in the file header (it's only used in executable files). - Auxiliary symbol records have the same width as a symbol table entry. Since symbol table entries are bigger, so are auxiliary symbol records. Write support will come soon. Differential Revision: http://reviews.llvm.org/D5259 llvm-svn: 217496
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