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* [X86] Add broadcast load folding patterns to NoVLX ↵Craig Topper2019-10-031-7/+31
| | | | | | | | VPMULLQ/VPMAXSQ/VPMAXUQ/VPMINSQ/VPMINUQ patterns. More fixes for PR36191. llvm-svn: 373560
* [X86] Remove a couple redundant isel patterns that look to have been ↵Craig Topper2019-10-031-17/+0
| | | | | | copy/pasted from right above them. NFC llvm-svn: 373559
* [gicombiner] Fix windows issue where single quotes in the command are passed ↵Daniel Sanders2019-10-021-1/+1
| | | | | | through to tablegen llvm-svn: 373545
* [AMDGPU] Fix illegal agpr use by VALUStanislav Mekhanoshin2019-10-021-1/+10
| | | | | | | | | | | | | | | | | | | When SIFixSGPRCopies attempts to fix an illegal copy from vector to scalar register it calls moveToVALU(). A copy from an agpr to sgpr becomes a copy from agpr to agpr, which may result in the illegal register class at a use of this copy. Solution is to copy it always into a vgpr. This may result in a subsequent copy into an agpr if that is what really needed, however should not happen too often and likely will be folded later. The opposite situation may not happen because an sgpr is always illegal where agpr is legal, so such user instructions may not exist. Differential Revision: https://reviews.llvm.org/D68358 llvm-svn: 373544
* [InstCombine] Bypass high bit extract before variable sign-extension (PR43523)Roman Lebedev2019-10-022-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | https://rise4fun.com/Alive/8BY - valid for lshr+trunc+variable sext https://rise4fun.com/Alive/7jk - the variable sext can be redundant https://rise4fun.com/Alive/Qslu - 'exact'-ness of first shift can be preserver https://rise4fun.com/Alive/IF63 - without trunc we could view this as more general "drop redundant mask before right-shift", but let's handle it here for now https://rise4fun.com/Alive/iip - likewise, without trunc, variable sext can be redundant. There's more patterns for sure - e.g. we can have 'lshr' as the final shift, but that might be best handled by some more generic transform, e.g. "drop redundant masking before right-shift" (PR42456) I'm singling-out this sext patch because you can only extract high bits with `*shr` (unlike abstract bit masking), and i *know* this fold is wanted by existing code. I don't believe there is much to review here, so i'm gonna opt into post-review mode here. https://bugs.llvm.org/show_bug.cgi?id=43523 llvm-svn: 373542
* DebugInfo: Rename DebugLocStream::Entry::Begin/EndSym to just Begin/EndDavid Blaikie2019-10-022-17/+13
| | | | | | | | Brings this struct in line with the RangeSpan class so they might eventually be used by common template code for generating range/loc lists with less duplicate code. llvm-svn: 373540
* [InstCombine] Transform bcopy to memmoveDavid Bolvansky2019-10-021-0/+8
| | | | | | | bcopy is still widely used mainly for network apps. Sadly, LLVM has no optimizations for bcopy, but there are some for memmove. Since bcopy == memmove, it is profitable to transform bcopy to memmove and use current optimizations for memmove for free here. llvm-svn: 373537
* [LegalizeTypes] Check for already split condition before calilng ↵Craig Topper2019-10-021-4/+4
| | | | | | | | SplitVecRes_SETCC in SplitRes_SELECT. No point in manually splitting the SETCC if it was already done. llvm-svn: 373535
* DebugInfo: Simplify RangeSpan to be a plain structDavid Blaikie2019-10-023-21/+15
| | | | | | | | | | | | | | This is an effort to make RangeSpan and DebugLocStream::Entry more similar to share code for their emission (to reuse the more complicated code for using (& choosing when to use) base address selection entries, etc). It didn't seem like this struct was worth the complexity of encapsulation - when the members could be initialized by the ctor to any value (no validation) and the type is assignable (so there's no mutability or other constraint being implemented by its interface). llvm-svn: 373533
* [gicombiner] Add the boring boilerplate for the declarative combinerDaniel Sanders2019-10-024-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first of a series of patches extracted from a much bigger WIP patch. It merely establishes the tblgen pass and the way empty combiner helpers are declared and integrated into a combiner info. The tablegen pass takes a -combiners option to select the combiner helper that will be generated. This can be given multiple values to generate multiple combiner helpers at once. Doing so helps to minimize parsing overhead. The reason for creating a GlobalISel subdirectory in utils/TableGen is that there will be quite a lot of non-pass files (~15) by the time the patch series is done. Reviewers: volkan Subscribers: mgorny, hiraditya, simoncook, Petar.Avramovic, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68286 llvm-svn: 373527
* Recommit "[GlobalOpt] Pass DTU to removeUnreachableBlocks instead of ↵Florian Hahn2019-10-021-7/+3
| | | | | | | | | | | recomputing." The cause for the revert should be fixed by r373513 / a80b6c15425f82521c624ff24c5c0a34cd534d54 This reverts commit 47dbcbd8ec6bf6c0b9cbe5811e81a37cc55e73ef. llvm-svn: 373522
* [PowerPC] Fix SH field overflow issueYi-Hong Lyu2019-10-021-4/+8
| | | | | | | | | | Store rlwinm Rx, Ry, 32, 0, 31 as rlwinm Rx, Ry, 0, 0, 31 and store rldicl Rx, Ry, 64, 0 as rldicl Rx, Ry, 0, 0. Otherwise SH field is overflow and fails assertion in assembly printing stage. Differential Revision: https://reviews.llvm.org/D66991 llvm-svn: 373519
* Handle llvm.launder.invariant.group in msan.Evgeniy Stepanov2019-10-021-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: [MSan] handle llvm.launder.invariant.group Msan used to give false-positives in class Foo { public: virtual ~Foo() {}; }; // Return true iff *x is set. bool f1(void **x, bool flag); Foo* f() { void *p; bool found; found = f1(&p,flag); if (found) { // p is always set here. return static_cast<Foo*>(p); // False positive here. } return nullptr; } Patch by Ilya Tokar. Reviewers: #sanitizers, eugenis Reviewed By: #sanitizers, eugenis Subscribers: eugenis, Prazek, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68236 llvm-svn: 373515
* [Local] Handle terminators with users in removeUnreachableBlocks.Florian Hahn2019-10-021-3/+7
| | | | | | | | | | | | | | | | Terminators like invoke can have users outside the current basic block. We have to replace those users with undef, before replacing the terminator. This fixes a crash exposed by rL373430. Reviewers: brzycki, asbirlea, davide, spatel Reviewed By: asbirlea Differential Revision: https://reviews.llvm.org/D68327 llvm-svn: 373513
* [MemorySSA] Update Phi creation when inserting a Def.Alina Sbirlea2019-10-021-37/+40
| | | | | | | | | MemoryPhis should be added in the IDF of the blocks newly gaining Defs. This includes the blocks that gained a Phi and the block gaining a Def, if the block did not have one before. Resolves PR43427. llvm-svn: 373505
* [ARM] Make helpers static. NFC.Benjamin Kramer2019-10-021-3/+5
| | | | llvm-svn: 373503
* [X86] Rewrite to the vXi1 subvector insertion code to not rely on the value ↵Craig Topper2019-10-021-14/+26
| | | | | | | | | | | | | | of bits that might be undef The previous code tried to do a trick where we would extract the subvector from the location we were inserting. Then xor that with the new value. Take the xored value and clear out the bits above the subvector size. Then shift that xored subvector to the insert location. And finally xor that with the original vector. Since the old subvector was used in both xors, this would leave just the new subvector at the inserted location. Since the surrounding bits had been zeroed no other bits of the original vector would be modified. Unfortunately, if the old subvector came from undef we might aggressively propagate the undef. Then we end up with the XORs not cancelling because they aren't using the same value for the two uses of the old subvector. @bkramer gave me a case that demonstrated this, but we haven't reduced it enough to make it easily readable to see what's happening. This patch uses a safer, but more costly approach. It isolate the bits above the insertion and bits below the insert point and ORs those together leaving 0 for the insertion location. Then widens the subvector with 0s in the upper bits, shifts it into position with 0s in the lower bits. Then we do another OR. Differential Revision: https://reviews.llvm.org/D68311 llvm-svn: 373495
* Fix: Actually erase remove the elements from AssumeHandlesAditya Kumar2019-10-021-1/+4
| | | | | | | | | | | | | | Reviewers: sdmitriev, tejohnson Reviewed by: tejohnson Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68318 llvm-svn: 373494
* [WebAssembly] Error when using wasm64 for ISelThomas Lively2019-10-021-0/+6
| | | | | | | | | | | | | | | | | | | | Summary: 64-bit WebAssembly (wasm64) is not specified and not supported in the WebAssembly backend. We do have support for it in clang, however, and we would like to keep that support because we expect wasm64 to be specified and supported in the future. For now add an error when trying to use wasm64 from the backend to minimize user confusion from unexplained crashes. Reviewers: aheejin, dschuff, sunfish Subscribers: sbc100, jgravelle-google, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68254 llvm-svn: 373493
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-0214-155/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
* [Local] Remove unused LazyValueInfo pointer from removeUnreachableBlock.Florian Hahn2019-10-022-8/+4
| | | | | | | | | | | | | There are no users that pass in LazyValueInfo, so we can simplify the function a bit. Reviewers: brzycki, asbirlea, davide Reviewed By: davide Differential Revision: https://reviews.llvm.org/D68297 llvm-svn: 373488
* [ThinLTO/WPD] Ensure devirtualized targets use promoted symbol when necessaryTeresa Johnson2019-10-022-9/+8
| | | | | | | | | | | | | | | | | | | | Summary: This fixes a hole in the handling of devirtualized targets that were local but need promoting due to devirtualization in another module. We were not correctly referencing the promoted symbol in some cases. Make sure the code that updates the name also looks at the ExportedGUIDs set by utilizing a callback that checks all conditions (the callback utilized by the internalization/promotion code). Reviewers: pcc, davidxl, hiraditya Subscribers: mehdi_amini, Prazek, inglorion, steven_wu, dexonsmith, dang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68159 llvm-svn: 373485
* [CodeGen] Remove unused MachineMemOperand::print wrappers (PR41772)Simon Pilgrim2019-10-021-11/+0
| | | | | | | | | | As noted on PR41772, the static analyzer reports that the MachineMemOperand::print partial wrappers set a number of args to null pointers that were then dereferenced in the actual implementation. It turns out that these wrappers are not being used at all (hence why we're not seeing any crashes), so I'd like to propose we just get rid of them. Differential Revision: https://reviews.llvm.org/D68208 llvm-svn: 373484
* LowerExpectIntrinsic handlePhiDef - silence static analyzer ↵Simon Pilgrim2019-10-021-1/+1
| | | | | | | | dyn_cast<PHINode> null dereference warning. NFCI. The static analyzer is warning about a potential null dereference, but we should be able to use cast<PHINode> directly and if not assert will fire for us. llvm-svn: 373481
* [CodeExtractor] NFC: Refactor sanity checks into isEligibleAditya Kumar2019-10-021-24/+31
| | | | | | | | | | | | Reviewers: fhahn Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68331 llvm-svn: 373479
* Reapply r373431 "Switch lowering: omit range check for bit tests when ↵Hans Wennborg2019-10-021-18/+25
| | | | | | | | | | | | | | | | | default is unreachable (PR43129)" This was reverted in r373454 due to breaking the expensive-checks bot. This version addresses that by omitting the addSuccessorWithProb() call when omitting the range check. > Switch lowering: omit range check for bit tests when default is unreachable (PR43129) > > This is modeled after the same functionality for jump tables, which was > added in r357067. > > Differential revision: https://reviews.llvm.org/D68131 llvm-svn: 373477
* [yaml2obj] - Alow Size tag for describing SHT_HASH sections.George Rimar2019-10-022-7/+14
| | | | | | | | | This is a follow-up for D68085 which allows using "Size" tag together with "Content" tag or alone. Differential revision: https://reviews.llvm.org/D68216 llvm-svn: 373473
* [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsicKerry McLaughlin2019-10-022-6/+16
| | | | | | | | | | | | | | | | Summary: This patch includes tests for the VecOfBitcastsToInt type added by D68021 Reviewers: c-rhodes, sdesmalen, rovka Reviewed By: c-rhodes Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits, cfe-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68023 llvm-svn: 373468
* MemorySSAUpdater::applyInsertUpdates - silence static analyzer ↵Simon Pilgrim2019-10-021-1/+1
| | | | | | | | dyn_cast<MemoryAccess> null dereference warning. NFCI. The static analyzer is warning about a potential null dereference, but we should be able to use cast<MemoryAccess> directly and if not assert will fire for us. llvm-svn: 373467
* MemorySSA tryOptimizePhi - assert that we've found a DefChainEnd. NFCI.Simon Pilgrim2019-10-021-0/+1
| | | | | | Silences static analyzer null dereference warning. llvm-svn: 373466
* LoopAccessAnalysis isConsecutiveAccess() - silence static analyzer ↵Simon Pilgrim2019-10-021-2/+2
| | | | | | | | dyn_cast<SCEVConstant> null dereference warning. NFCI. The static analyzer is warning about potential null dereferences, but in these cases we should be able to use cast<SCEVConstant> directly and if not assert will fire for us. llvm-svn: 373465
* AsmPrinter - emitGlobalConstantFP - silence static analyzer null dereference ↵Simon Pilgrim2019-10-021-5/+2
| | | | | | | | warning. NFCI. All the calls to emitGlobalConstantFP should provide a nonnull Type for the float. llvm-svn: 373464
* [ModuloSchedule] Peel out prologs and epilogs, generate actual codeJames Molloy2019-10-024-4/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This extends the PeelingModuloScheduleExpander to generate prolog and epilog code, and correctly stitch uses through the prolog, kernel, epilog DAG. The key concept in this patch is to ensure that all transforms are *local*; only a function of a block and its immediate predecessor and successor. By defining the problem in this way we can inductively rewrite the entire DAG using only local knowledge that is easy to reason about. For example, we assume that all prologs and epilogs are near-perfect clones of the steady-state kernel. This means that if a block has an instruction that is predicated out, we can redirect all users of that instruction to that equivalent instruction in our immediate predecessor. As all blocks are clones, every instruction must have an equivalent in every other block. Similarly we can make the assumption by construction that if a value defined in a block is used outside that block, the only possible user is its immediate successors. We maintain this even for values that are used outside the loop by creating a limited form of LCSSA. This code isn't small, but it isn't complex. Enabled a bunch of testing from Hexagon. There are a couple of tests not enabled yet; I'm about 80% sure there isn't buggy codegen but the tests are checking for patterns that we don't produce. Those still need a bit more investigation. In the meantime we (Google) are happy with the code produced by this on our downstream SMS implementation, and believe it generates correct code. Subscribers: mgorny, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68205 llvm-svn: 373462
* [InstCombine] Simplify fma multiplication to nan for undef or nan operands.Florian Hahn2019-10-021-3/+3
| | | | | | | | | | | | | | | | | In similar fashion to D67721, we can simplify FMA multiplications if any of the operands is NaN or undef. In instcombine, we will simplify the FMA to an fadd with a NaN operand, which in turn gets folded to NaN. Note that this just changes SimplifyFMAFMul, so we still not catch the case where only the Add part of the FMA is Nan/Undef. Reviewers: cameron.mcinally, mcberg2017, spatel, arsenm Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D68265 llvm-svn: 373459
* NFC: directly return when CommonExitBlock != SuccAditya Kumar2019-10-021-4/+2
| | | | | | | | | | Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68330 llvm-svn: 373456
* [InstSimplify] fold fma/fmuladd with a NaN or undef operandSanjay Patel2019-10-021-0/+9
| | | | | | | | | | | This is intended to be similar to the constant folding results from D67446 and earlier, but not all operands are constant in these tests, so the responsibility for folding is left to InstSimplify. Differential Revision: https://reviews.llvm.org/D67721 llvm-svn: 373455
* Revert r373431 "Switch lowering: omit range check for bit tests when default ↵Hans Wennborg2019-10-021-23/+17
| | | | | | | | | | | | | | | is unreachable (PR43129)" This broke http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19967 > Switch lowering: omit range check for bit tests when default is unreachable (PR43129) > > This is modeled after the same functionality for jump tables, which was > added in r357067. > > Differential revision: https://reviews.llvm.org/D68131 llvm-svn: 373454
* LICM - remove unused variable and reduce scope of another variable. NFCI.Simon Pilgrim2019-10-021-4/+2
| | | | | | Appeases both clang static analyzer and cppcheck llvm-svn: 373453
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-10-021-1/+1
| | | | llvm-svn: 373450
* WinException::emitExceptHandlerTable - silence static analyzer ↵Simon Pilgrim2019-10-021-2/+1
| | | | | | | | dyn_cast<Function> null dereference warning. NFCI. The static analyzer is warning about a potential null dereference, but we should be able to use cast<Function> directly and if not assert will fire for us. llvm-svn: 373449
* MetadataLoader upgradeCUVariables() - silence static analyzer ↵Simon Pilgrim2019-10-021-1/+1
| | | | | | | | dyn_cast_or_null<> null dereference warning. NFCI. The static analyzer is warning about a potential null dereference, but we know that the source won't be null so just use dyn_cast, which will assert if the value somehow is actually null. llvm-svn: 373448
* [ARM] Identity shuffles are legalDavid Green2019-10-021-0/+1
| | | | | | | | | | | | | | | Identity shuffles, of the form (0, 1, 2, 3, ...) are perfectly OK under MVE (they essentially just become bitcasts). We were not catching that in the existing set of what we considered legal though. On NEON, they would be covered by vext's, but that is not generally available in MVE. This uses ShuffleVectorInst::isIdentityMask which is a little odd to use here but does what we want and prevents us from just rewriting what is the same function. Differential Revision: https://reviews.llvm.org/D68241 llvm-svn: 373446
* [Support, ARM64] Define getHostCPUFeatures for Windows on ARM64 platformMartin Storsjo2019-10-021-0/+11
| | | | | | | | Patch by Adam Kallai! Differential Revision: https://reviews.llvm.org/D68139 llvm-svn: 373445
* [IntrinsicEmitter] Add overloaded type VecOfBitcastsToInt for SVE intrinsicsKerry McLaughlin2019-10-021-1/+23
| | | | | | | | | | | | | | | | | | | | | Summary: This allows intrinsics such as the following to be defined: - declare <n x 4 x i32> @llvm.something.nxv4f32(<n x 4 x i32>, <n x 4 x i1>, <n x 4 x float>) ...where <n x 4 x i32> is derived from <n x 4 x float>, but the element needs bitcasting to int. Reviewers: c-rhodes, sdesmalen, rovka Reviewed By: c-rhodes Subscribers: tschuett, hiraditya, jdoerfert, llvm-commits, cfe-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68021 llvm-svn: 373437
* Remove an unnecessary cast. NFC.Jay Foad2019-10-021-3/+2
| | | | llvm-svn: 373434
* [AMDGPU] Make printf lowering faster when there are no printfsJay Foad2019-10-021-16/+14
| | | | | | | | | | | | | | | | | Summary: Printf lowering unconditionally visited every instruction in the module. To make it faster in the common case where there are no printfs, look up the printf function (if any) and iterate over its users instead. Reviewers: rampitec, kzhuravl, alex-t, arsenm Subscribers: jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68145 llvm-svn: 373433
* Revert [GlobalOpt] Pass DTU to removeUnreachableBlocks instead of recomputing.Florian Hahn2019-10-021-3/+7
| | | | | | | | This breaks http://lab.llvm.org:8011/builders/sanitizer-windows/builds/52310 This reverts r373430 (git commit 70f70035484ba199a329f9f8d9bd67e37bc2b408) llvm-svn: 373432
* Switch lowering: omit range check for bit tests when default is unreachable ↵Hans Wennborg2019-10-021-17/+23
| | | | | | | | | | | (PR43129) This is modeled after the same functionality for jump tables, which was added in r357067. Differential revision: https://reviews.llvm.org/D68131 llvm-svn: 373431
* [GlobalOpt] Pass DTU to removeUnreachableBlocks instead of recomputing.Florian Hahn2019-10-021-7/+3
| | | | | | | | | | | | | removeUnreachableBlocks knows how to preserve the DomTree, so make use of it instead of re-computing the DT. Reviewers: davide, kuhar, brzycki Reviewed By: davide, kuhar Differential Revision: https://reviews.llvm.org/D68298 llvm-svn: 373430
* [Local] Simplify function removeUnreachableBlocks() to avoid (re-)computation.Florian Hahn2019-10-021-16/+10
| | | | | | | | | | | | | | | | | | Two small changes in llvm::removeUnreachableBlocks() to avoid unnecessary (re-)computation. First, replace the use of count() with find(), which has better time complexity. Second, because we have already computed the set of dead blocks, replace the second loop over all basic blocks to a loop only over the already computed dead blocks. This simplifies the loop and avoids recomputation. Patch by Rodrigo Caetano Rocha <rcor.cs@gmail.com> Reviewers: efriedma, spatel, fhahn, xbolva00 Reviewed By: fhahn, xbolva00 Differential Revision: https://reviews.llvm.org/D68191 llvm-svn: 373429
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