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* [CodeView] Hook up CodeViewRecordIO to type serialization path.Zachary Turner2016-11-0815-947/+485
| | | | | | | | | | | | Previously support had been added for using CodeViewRecordIO to read (deserialize) CodeView type records. This patch adds support for writing those same records. With this patch, reading and writing of CodeView type records finally uses a single codepath. Differential Revision: https://reviews.llvm.org/D26253 llvm-svn: 286304
* Emit the DW_AT_type for a C++ static member definitionAdrian Prantl2016-11-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | if it is more specific than the one in its DW_AT_specification. If a static member is an array, the translation unit containing the member definition may have a more specific type (including its length) than TUs only seeing the class declaration. This patch adds a DW_AT_type to the member's DW_TAG_variable in addition to the DW_AT_specification in these cases. The member type in the DW_AT_specification still shows the more generic type (without the length) to avoid defeating type uniquing. The DWARF standard discourages “duplicating” a DW_AT_type in a member variable definition but doesn’t explicitly forbid it. Having the more specific type (with the array length) available is what allows the debugger to print the contents of a static array member variable. https://reviews.llvm.org/D26368 rdar://problem/28706946 llvm-svn: 286302
* GlobalISel: make sure debugging variables are appropriately elided in ↵David L. Jones2016-11-081-2/+4
| | | | | | | | | | | | | | | | release builds. Summary: There are two variables here that break. This change constrains both of them to debug builds (via DEBUG() or #ifndef NDEBUG). Reviewers: bkramer, t.p.northover Subscribers: mehdi_amini, vkalintiris Differential Revision: https://reviews.llvm.org/D26421 llvm-svn: 286300
* [ThinLTO] Prevent exporting of locals used/defined in module level asmTeresa Johnson2016-11-084-13/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch uses the same approach added for inline asm in r285513 to similarly prevent promotion/renaming of locals used or defined in module level asm. All static global values defined in normal IR and used in module level asm should be included on either the llvm.used or llvm.compiler.used global. The former were already being flagged as NoRename in the summary, and I've simply added llvm.compiler.used values to this handling. Module level asm may also contain defs of values. We need to prevent export of any refs to local values defined in module level asm (e.g. a ref in normal IR), since that also requires renaming/promotion of the local. To do that, the summary index builder looks at all values in the module level asm string that are not marked Weak or Global, which is exactly the set of locals that are defined. A summary is created for each of these local defs and flagged as NoRename. This required adding handling to the BitcodeWriter to look at GV declarations to see if they have a summary (rather than skipping them all). Finally, added an assert to IRObjectFile::CollectAsmUndefinedRefs to ensure that an MCAsmParser is available, otherwise the module asm parse would silently fail. Initialized the asm parser in the opt tool for use in testing this fix. Fixes PR30610. Reviewers: mehdi_amini Subscribers: johanengelen, krasin, llvm-commits Differential Revision: https://reviews.llvm.org/D26146 llvm-svn: 286297
* [asan] Speed up compilation of large C++ stringmaps (tons of allocas) with ASanKuba Brecka2016-11-081-6/+12
| | | | | | | | This addresses PR30746, <https://llvm.org/bugs/show_bug.cgi?id=30746>. The ASan pass iterates over entry-block instructions and checks each alloca whether it's in NonInstrumentedStaticAllocaVec, which is apparently slow. This patch gathers the instructions to move during visitAllocaInst. Differential Revision: https://reviews.llvm.org/D26380 llvm-svn: 286296
* [BasicAA] Teach BasicAA to handle the inaccessiblememonly and ↵Andrew Kaylor2016-11-082-2/+7
| | | | | | | | inaccessiblemem_or_argmemonly attributes Differential Revision: https://reviews.llvm.org/D26382 llvm-svn: 286294
* AArch64DeadRegisterDefinitionsPass: Fix Changed flagMatthias Braun2016-11-081-1/+0
| | | | | | Fix a bug in the calculation of the changed flag introduced in r285488. llvm-svn: 286293
* [TBAA] Drop support for "old style" scalar TBAA tagsSanjoy Das2016-11-082-57/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We've had support for auto upgrading old style scalar TBAA access metadata tags into the "new" struct path aware TBAA metadata for 3 years now. The only way to actually generate old style TBAA was explicitly through the IRBuilder API. I think this is a good time for dropping support for old style scalar TBAA. I'm not removing support for textual or bitcode upgrade -- if you have IR with the old style scalar TBAA tags that go through the AsmParser orf the bitcode parser before LLVM sees them, they will keep working as usual. Note: %val = load i32, i32* %ptr, !tbaa !N !N = < scalar tbaa node > is equivalent to %val = load i32, i32* %ptr, !tbaa !M !N = < scalar tbaa node > !M = !{!N, !N, 0} Reviewers: manmanren, chandlerc, sunfish Subscribers: mcrosier, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D26229 llvm-svn: 286291
* GlobalISel: allow CodeGen to fallback on VReg type/class issues.Tim Northover2016-11-082-25/+38
| | | | | | | | | After instruction selection we perform some checks on each VReg just before discarding the type information. These checks were assertions before, but that breaks the fallback path so this patch moves the logic into the main flow and reports a better error on failure. llvm-svn: 286289
* [SystemZ] Add missing FP extension instructionsUlrich Weigand2016-11-084-18/+42
| | | | | | | | This completes assembler / disassembler support for all BFP instructions provided by the floating-point extensions facility. The instructions added here are not currently used for codegen. llvm-svn: 286285
* [SystemZ] Add program mask and addressing mode instructionsUlrich Weigand2016-11-085-11/+109
| | | | | | | | | Add several instructions that operate on the program mask or the addressing mode. These are not really needed for code generation under Linux, but are provided for completeness for the assembler/disassembler. llvm-svn: 286284
* [SystemZ] Model access registers as LLVM registersUlrich Weigand2016-11-0817-102/+126
| | | | | | | | | | | | | Add the 16 access registers as LLVM registers. This allows removing a lot of special cases in the assembler and disassembler where we were handling access registers; this can all just use the generic register code now. Also add a bunch of instructions to operate on access registers, for assembler/disassembler use only. No change in code generation intended. llvm-svn: 286283
* [LoopDistribute] Preserve GlobalsAA also in the new Pass Manager.Davide Italiano2016-11-081-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D26408 llvm-svn: 286280
* Don't store Twine in a local variable.Eli Friedman2016-11-081-2/+1
| | | | | | Fixes post-commit review comment from r286177. llvm-svn: 286275
* [WebAssembly] Convert stackified IMPLICIT_DEF into constant 0.Dan Gohman2016-11-081-0/+37
| | | | | | | | | | Since IMPLIFIT_DEF instructions are omitted in the output, when the output of an IMPLICIT_DEF instruction is stackified, the resulting register lacks an explicit push, leading to a push/pop mismatch. Fix this by converting such IMPLICIT_DEFs into CONST_I32 0 instructions so that they have explicit pushes. llvm-svn: 286274
* [GlobalISel] Dump all instructions inserted by selector.Ahmed Bougacha2016-11-081-3/+9
| | | | | | This is helpful when multiple instructions are inserted. llvm-svn: 286273
* [GlobalISel] Permit select() to erase.Ahmed Bougacha2016-11-081-5/+22
| | | | | | | | | | | Erasing reverse_iterators is problematic; iterate manually. While there, keep track of the range of inserted instructions. It can miss instructions inserted elsewhere, but those are harder to track. Differential Revision: http://reviews.llvm.org/D22924 llvm-svn: 286272
* [LibcallsShrinkWrap] This pass doesn't preserve the CFG.Davide Italiano2016-11-081-2/+5
| | | | | | | | | | For example, it invalidates the domtree, causing assertions in later passes which need dominator infos. Make it preserve GlobalsAA, as suggested by Eli. Differential Revision: https://reviews.llvm.org/D26381 llvm-svn: 286271
* Fix typo in comment. NFC.Chad Rosier2016-11-081-2/+2
| | | | llvm-svn: 286270
* [SystemZ] Always use semantic instruction classesUlrich Weigand2016-11-083-96/+190
| | | | | | | | | | Define a couple of additional semantic classes and use them throughout the .td files to make them more consistent and more easily readable. No functional change. llvm-svn: 286268
* [SystemZ] Refactor InstRR* instruction format patternsUlrich Weigand2016-11-083-227/+260
| | | | | | | | | | | | | | | This changes the InstRR (and related) patterns to no longer automatically add an "r" at the end of the mnemonic. This makes the .td files more obviously understandable, and also allows using the patterns for those few instructions that do not follow the *r scheme. Also add some more sub-formats of the RRF format class, to match operand names and sequence from the PoP better. No functional change. llvm-svn: 286267
* [SystemZ] Rename some Inst* instruction format classesUlrich Weigand2016-11-082-96/+96
| | | | | | | | | | | Now that we've added instruction format subclasses like InstRIb, it makes sense to rename the old InstRI to InstRIa. Similar for InstRX, InstRXY, InstRS, InstRSY, and InstSS. No functional change. llvm-svn: 286266
* [MC][AArch64] Cleanup end-of-line parsing in AArch64 AsmParser.Nirav Dave2016-11-081-222/+136
| | | | | | | | | | Reviewers: t.p.northover, rengolin Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D26309 llvm-svn: 286265
* [SystemZ] Refactor branch and conditional instruction patternsUlrich Weigand2016-11-086-615/+978
| | | | | | | | | | | | | | | | | Rework patterns for branches, call & return instructions, compare-and-branch, compare-and-trap, and conditional move instructions. In particular, simplify creation of patterns for the extended opcodes of instructions that take a CC mask. Also, use semantical instruction classes for all the instructions instead of open-coding them in SystemZInstrInfo.td. Adds a couple of the basic branch instructions (that are unused for codegen) for the assembler/disassembler. llvm-svn: 286263
* NFC small changes in MemDepPiotr Padlewski2016-11-081-3/+3
| | | | llvm-svn: 286260
* [RegAllocGreedy] Another fix about NewVRegs for last chance recoloring after ↵Wei Mi2016-11-081-8/+5
| | | | | | | | | | | | | | | | | | r281783. About when we should move a vreg from CurrentNewVRegs to NewVRegs, if the vreg in CurrentNewVRegs was added into RecoloringCandidate and was evicted, it shouldn't be added to NewVRegs because its physical register will be restored at the end of tryLastChanceRecoloring after the recoloring failed. If the vreg in CurrentNewVRegs was not in RecoloringCandidate, i.e. it was evicted in selectOrSplitImpl inside tryRecoloringCandidates, its physical register will not be restored even if the recoloring failed. In that case, we need to add the vreg to NewVRegs. Same as r281783, the problem was seen on out-of-tree target and we didn't have a test case that reproduce the problem with in-tree targets. llvm-svn: 286259
* GlobalISel: support selecting fpext/fptrunc instructions on AArch64.Tim Northover2016-11-081-0/+54
| | | | llvm-svn: 286253
* Fix PR27500: on MSP430 the branch destination offset is measured in words, ↵Anton Korobeynikov2016-11-081-115/+191
| | | | | | | | | | | | | | not bytes. Summary: In addition, the branch instructions will have proper BB destinations, not offsets, like before. Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23718 llvm-svn: 286252
* Remove unused include. NFC.Chad Rosier2016-11-081-1/+0
| | | | llvm-svn: 286250
* Use the last 7 bits to represent the discriminator to fit it in 1 byte ↵Dehao Chen2016-11-081-5/+7
| | | | | | | | ULEB128 (NFC). From experiments, discriminator is rarely greater than 127. Here we enforce it to be no greater than 127 so that it will always fit in 1 byte. llvm-svn: 286245
* [TargetLowering] Fix undef vector element issue with true/false result handlingSimon Pilgrim2016-11-081-10/+10
| | | | | | | | | | | | | | Fixed an issue with vector usage of TargetLowering::isConstTrueVal / TargetLowering::isConstFalseVal boolean result matching. The comment said we shouldn't handle constant splat vectors with undef elements. But the the actual code was returning false if the build vector contained no undef elements.... This patch now ignores the number of undefs (getConstantSplatNode will return null if the build vector is all undefs). The change has also unearthed a couple of missed opportunities in AVX512 comparison code that will need to be addressed. Differential Revision: https://reviews.llvm.org/D26031 llvm-svn: 286238
* [JumpThreading] Unfold selects that depend on the same conditionPablo Barrio2016-11-081-38/+77
| | | | | | | | | | | | | | | | | | Summary: These are good candidates for jump threading. This enables later opts (such as InstCombine) to combine instructions from the selects with instructions out of the selects. SimplifyCFG will fold the select again if unfolding wasn't worth it. Patch by James Molloy and Pablo Barrio. Reviewers: rengolin, haicheng, sebpop Subscribers: jojo, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D26391 llvm-svn: 286236
* [VectorLegalizer] Expansion of CTLZ using CTPOP when possibleSimon Pilgrim2016-11-082-7/+54
| | | | | | | | | | This patch avoids scalarization of CTLZ by instead expanding to use CTPOP (ref: "Hacker's Delight") when the necessary operations are available. This also adds the necessary cost models for X86 SSE2 targets (the main beneficiary) to ensure vectorization only happens when its useful. Differential Revision: https://reviews.llvm.org/D25910 llvm-svn: 286233
* [AArch64] Fix incorrect CSEL node createdRoger Ferrer Ibanez2016-11-081-2/+3
| | | | | | | | | | | | Under -enable-unsafe-fp-math, SELECT_CC lowering in AArch64 transforms floating point comparisons of the form "a == 0.0 ? 0.0 : x" to "a == 0.0 ? a : x". But it incorrectly assumes that 'x' and 'a' have the same type which can lead to a wrong CSEL node that crashes later due to nonsensical copies. Differential Revision: https://reviews.llvm.org/D26394 llvm-svn: 286231
* Adds the loop end location to the loop metadata.Amara Emerson2016-11-081-7/+24
| | | | | | | | | | This additional information can be used to improve the locations when generating remarks for loops. Patch by Florian Hahn. Differential Revision: https://reviews.llvm.org/D25763 llvm-svn: 286227
* Fix memory leaks (coverity issues 1365586 & 1365591)Sylvestre Ledru2016-11-081-2/+6
| | | | | | | | | | Reviewers: hfinkel Subscribers: george.burgess.iv, malcolm.parsons, boris.ulasevich, llvm-commits Differential Revision: https://reviews.llvm.org/D26347 llvm-svn: 286223
* IR, Bitcode: Change bitcode reader to no longer own its memory buffer.Peter Collingbourne2016-11-088-128/+67
| | | | | | | | | | | | | | | | | | Unique ownership is just one possible ownership pattern for the memory buffer underlying the bitcode reader. In practice, as this patch shows, ownership can often reside at a higher level. With the upcoming change to allow multiple modules in a single bitcode file, it will no longer be appropriate for modules to generally have unique ownership of their memory buffer. The C API exposes the ownership relation via the LLVMGetBitcodeModuleInContext and LLVMGetBitcodeModuleInContext2 functions, so we still need some way for the module to own the memory buffer. This patch does so by adding an owned memory buffer field to Module, and using it in a few other places where it is convenient. Differential Revision: https://reviews.llvm.org/D26384 llvm-svn: 286214
* Bitcode: Decouple block info block state from reader.Peter Collingbourne2016-11-082-35/+29
| | | | | | | | | | | | | | | | | As proposed on llvm-dev: http://lists.llvm.org/pipermail/llvm-dev/2016-October/106630.html Move block info block state to a new class, BitstreamBlockInfo. Clients may set the block info for a particular cursor with the BitstreamCursor::setBlockInfo() method. At this point BitstreamReader is not much more than a container for an ArrayRef<uint8_t>, so remove it and replace all uses with direct uses of memory buffers. Differential Revision: https://reviews.llvm.org/D26259 llvm-svn: 286207
* Bitcode: Split out block info reading into a separate function.Peter Collingbourne2016-11-081-2/+8
| | | | | | We're about to make this more complicated. llvm-svn: 286206
* Add a missing break statement. NFC.George Burgess IV2016-11-081-0/+1
| | | | llvm-svn: 286203
* GlobalISel: improve error diagnostics when IRTranslation fails.Tim Northover2016-11-081-3/+9
| | | | llvm-svn: 286190
* GlobalISel: support selecting G_SELECT on AArch64.Tim Northover2016-11-081-0/+40
| | | | llvm-svn: 286185
* GlobalISel: constrain PHI registers on AArch64.Tim Northover2016-11-081-3/+33
| | | | | | | | | | Self-referencing PHI nodes need their destination operands to be constrained because nothing else is likely to do so. For now we just pick a register class naively. Patch mostly by Ahmed again. llvm-svn: 286183
* [LTO] Add error message on IO error in compileOptimizedToFile.Eli Friedman2016-11-071-0/+2
| | | | | | | | (No testcase because it's difficult to force an error here.) Differential Revision: https://reviews.llvm.org/D26371 llvm-svn: 286177
* [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition ↵Stanislav Mekhanoshin2016-11-072-5/+26
| | | | | | | | | | | | | | | | | | | | copies Codegen prepare sinks comparisons close to a user is we have only one register for conditions. For AMDGPU we have many SGPRs capable to hold vector conditions. Changed BE to report we have many condition registers. That way IR LICM pass would hoist an invariant comparison out of a loop and codegen prepare will not sink it. With that done a condition is calculated in one block and used in another. Current behavior is to store workitem's condition in a VGPR using v_cndmask and then restore it with yet another v_cmp instruction from that v_cndmask's result. To mitigate the issue a forward propagation of a v_cmp 64 bit result to an user is implemented. Additional side effect of this is that we may consume less VGPRs in a cost of more SGPRs in case if holding of multiple conditions is needed, and that is a clear win in most cases. llvm-svn: 286171
* [OptDiag, opt-viewer] Save callee's location and display as linkAdam Nemet2016-11-072-1/+10
| | | | | | | | | | | | | With this we get a new field in the YAML record if the value being streamed out has a debug location. For examples, please see the changes to the tests. This is then used in opt-viewer to display a link for the callee function in the inlining remarks. Differential Revision: https://reviews.llvm.org/D26366 llvm-svn: 286169
* [AArch64] Transfer memory operands when lowering vector load/store intrinsicsSanjin Sijaric2016-11-071-0/+11
| | | | | | | | | | | | | | | Summary: Some vector loads and stores generated from AArch64 intrinsics alias each other unnecessarily, preventing better scheduling. We just need to transfer memory operands during lowering. Reviewers: mcrosier, t.p.northover, jmolloy Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D26313 llvm-svn: 286168
* [TRE] Remove dead codeSanjoy Das2016-11-071-1/+0
| | | | | | Address review by Eli Friedman on rL286147. llvm-svn: 286165
* [WebAssembly] Emit a BasePointer when we have overly-aligned stack objectsDerek Schuff2016-11-073-10/+64
| | | | | | | | | | | | Because we shift the stack pointer by an unknown amount, we need an additional pointer. In the case where we have variable-size objects as well, we can't reuse the frame pointer, thus three pointers. Patch by Jacob Gravelle Differential Revision: https://reviews.llvm.org/D26263 llvm-svn: 286160
* Reset debug loc to OldInduction in ↵Dehao Chen2016-11-071-1/+3
| | | | | | | | InnerLoopVectorizer::createInductionVariable. (NFC) This is to prevent SetInsertionPoint from setting debug loc to Latch->getTerminator(). llvm-svn: 286159
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