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* Revert "[ObjectYAML] Support for DWARF debug_info section"Chris Bieneman2016-12-202-41/+4
| | | | | | | | This reverts commit r290147. This commit is breaking a bot (http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/621). I don't have time to investigate at the moment, so I'll revert for now. llvm-svn: 290148
* [ObjectYAML] Support for DWARF debug_info sectionChris Bieneman2016-12-202-4/+41
| | | | | | This patch adds support for YAML<->DWARF for debug_info sections. llvm-svn: 290147
* [LV] Sink tripcount query to where it's actually used. NFC.Michael Kuperstein2016-12-191-5/+4
| | | | llvm-svn: 290142
* [ObjectYAML] Support for DWARF Pub SectionsChris Bieneman2016-12-191-0/+30
| | | | | | This patch adds support for YAML<->DWARF round tripping for pub* section data. The patch supports both GNU and non-GNU style entries. llvm-svn: 290139
* [libfuzzer] dump_coverage command line flagMike Aizatsky2016-12-197-0/+28
| | | | | | | | Reviewers: kcc, vitalybuka Differential Revision: https://reviews.llvm.org/D27942 llvm-svn: 290138
* [TargetInstrInfo] replace redundant expression in getMemOpBaseRegImmOfsMichael LeMay2016-12-191-2/+1
| | | | | | | | | | | | | | | Summary: The expression for computing the return value of getMemOpBaseRegImmOfs has only one possible value. The other value would result in a return earlier in the function. This patch replaces the expression with its only possible value. Reviewers: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27437 llvm-svn: 290133
* Make a function to correctly extract the DW_AT_high_pc given the low pc value.Greg Clayton2016-12-191-13/+22
| | | | | | | | DWARF 4 and later supports encoding the PC as an address or as as offset from the low PC. Clients using DWARFDie should be insulated from how to extract the high PC value. This function takes care of extracting the form value and looking for the correct form. Differential Revision: https://reviews.llvm.org/D27885 llvm-svn: 290131
* [InstCombine] use commutative matcher for pattern with commutative operatorsSanjay Patel2016-12-191-3/+5
| | | | | | | | This is a case that was missed in: https://reviews.llvm.org/rL290067 ...and it would regress if we fix operand complexity (PR28296). llvm-svn: 290127
* [InstCombine] add folds for icmp (umin|umax X, Y), XSanjay Patel2016-12-191-19/+54
| | | | | | | | This is a follow-up to: https://reviews.llvm.org/rL289855 (https://reviews.llvm.org/D27531) https://reviews.llvm.org/rL290111 llvm-svn: 290118
* [LoopVersioning] Require loop-simplify form for loop versioning.Florian Hahn2016-12-194-14/+17
| | | | | | | | | | | | | | | | Summary: Requiring loop-simplify form for loop versioning ensures that the runtime check block always dominates the exit block. This patch closes #30958 (https://llvm.org/bugs/show_bug.cgi?id=30958). Reviewers: silviu.baranga, hfinkel, anemet, ashutosh.nema Subscribers: ashutosh.nema, mzolotukhin, efriedma, hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D27469 llvm-svn: 290116
* [AMDGPU] When unifying metadata, add operands to named metadata individuallyKonstantin Zhuravlyov2016-12-191-3/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D27725 llvm-svn: 290114
* [InstCombine] add folds for icmp (smax X, Y), XSanjay Patel2016-12-191-17/+35
| | | | | | | This is a follow-up to: https://reviews.llvm.org/rL289855 (D27531) llvm-svn: 290111
* Silence unused warning.Daniel Jasper2016-12-191-0/+1
| | | | llvm-svn: 290109
* [ARM] GlobalISel: Lower i8 and i16 register argsDiana Picus2016-12-191-5/+20
| | | | | | | | | | | This allows lowering i8 and i16 arguments if they can fit in the registers. Note that the lowering is incomplete - ABI extensions are handled in a subsequent patch. (Last part of) Differential Revision: https://reviews.llvm.org/D27704 llvm-svn: 290106
* [ARM] GlobalISel: Allow i8 and i16 addsDiana Picus2016-12-191-1/+6
| | | | | | | | | Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
* [ARM] GlobalISel: Select i8 and i16 copiesDiana Picus2016-12-191-2/+9
| | | | | | | | | Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
* [Power9] Processor Model for SchedulingEhsan Amiri2016-12-194-3/+1145
| | | | | | | | PWR9 processor model for instruction scheduling. A subsequent patch will migrate PWR9 to Post RA MIScheduler. https://reviews.llvm.org/D24525 llvm-svn: 290102
* [Hexagon] Restore minimum profit check accidentally changed in r290024Malcolm Parsons2016-12-191-2/+2
| | | | llvm-svn: 290100
* [ARM] GlobalISel: Lower more than 4 argumentsDiana Picus2016-12-191-10/+22
| | | | | | | | | | This adds support for lowering more than 4 arguments (although still i32 only). It uses the handleAssignments / ValueHandler infrastructure extracted from the AArch64 backend in r288658. Differential Revision: https://reviews.llvm.org/D27195 llvm-svn: 290098
* AMDGPU: [AMDGPU] Assembler: add .hsa_code_object_metadata directive for ↵Sam Kolton2016-12-194-72/+143
| | | | | | | | | | | | | | | | | | | | | | | | functime metadata V2.0 Summary: Added pair of directives .hsa_code_object_metadata/.end_hsa_code_object_metadata. Between them user can put YAML string that would be directly put to the generated note. E.g.: ''' .hsa_code_object_metadata { amd.MDVersion: [ 2, 0 ] } .end_hsa_code_object_metadata ''' Based on D25046 Reviewers: vpykhtin, nhaustov, yaxunl, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, mgorny, tony-tye Differential Revision: https://reviews.llvm.org/D27619 llvm-svn: 290097
* [ARM] GlobalISel: Support loading from the stackDiana Picus2016-12-193-10/+45
| | | | | | | | | | Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
* [CodeGen] Make MachineInstr::isIdenticalTo() symmetric.Bjorn Pettersson2016-12-191-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: MachineInstr::isIdenticalTo() is for some reason not symmetric when comparing bundles, which gives us the property: I1->isIdenticalTo(*I2) != I2->isIdenticalTo(*I1) when comparing bundles where one bundle is longer than the other. This patch makes sure that bundles of different length always are considered as not being identical. Thus, the result of the comparison will be the same regardless of which side that happens to be to the left. Reviewers: dexonsmith, jonpa, andrew.w.kaylor Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D27508 llvm-svn: 290095
* [XRay] Fix assertion failure on empty machine basic blocks (PR 31424)Dean Michael Berris2016-12-191-2/+9
| | | | | | | | | | | | | | | | | | | | The original version of the code in XRayInstrumentation.cpp assumed that functions may not have empty machine basic blocks (or that the first one couldn't be). This change addresses that by special-casing that specific situation. We provide two .mir test-cases to make sure we're handling this appropriately. Fixes llvm.org/PR31424. Reviewers: chandlerc Subscribers: varno, llvm-commits Differential Revision: https://reviews.llvm.org/D27913 llvm-svn: 290091
* [X86] When recognizing vector loads or VZEXT_LOAD in selectScalarSSELoad ↵Craig Topper2016-12-191-2/+2
| | | | | | make sure we pass the load's user rather than load itself to the second operand of IsLegalToFold. llvm-svn: 290089
* Add files I seem to have dropped in my revert (r290086).Daniel Jasper2016-12-191-0/+140
| | | | | | Sorry! llvm-svn: 290087
* Revert @llvm.assume with operator bundles (r289755-r289757)Daniel Jasper2016-12-1964-747/+973
| | | | | | | This creates non-linear behavior in the inliner (see more details in r289755's commit thread). llvm-svn: 290086
* [X86] Remove all of the patterns that use X86ISD:FAND/FXOR/FOR/FANDN except ↵Craig Topper2016-12-192-131/+42
| | | | | | | | for the ones needed for SSE1. Anything SSE2 or above uses the integer ISD opcode. This removes 11721 bytes from the DAG isel table or 2.2% llvm-svn: 290073
* [PDB] Don't use the long typeDavid Majnemer2016-12-181-1/+1
| | | | | | | | Long is not the same size across a number of the platforms we support. Use unsigned int here instead, it is more appropriate because overflow/wrap-around is possible and, in this case, expected. llvm-svn: 290068
* [InstCombine] use commutative matchers for patterns with commutative operatorsSanjay Patel2016-12-181-20/+35
| | | | | | | | | | | | | | | | | | | | | | | | Background/motivation - I was circling back around to: https://llvm.org/bugs/show_bug.cgi?id=28296 I made a simple patch for that and noticed some regressions, so added test cases for those with rL281055, and this is hopefully the minimal fix for just those cases. But as you can see from the surrounding untouched folds, we are missing commuted patterns all over the place, and of course there are no regression tests to cover any of those cases. We could sprinkle "m_c_" dust all over this file and catch most of the missing folds, but then we still wouldn't have test coverage, and we'd still miss some fraction of commuted patterns because they require adjustments to the match order. I'm aware of the concern about the potential compile-time performance impact of adding matches like this (currently being discussed on llvm-dev), but I don't think there's any evidence yet to suggest that handling commutative pattern matching more thoroughly is not a worthwhile goal of InstCombine. Differential Revision: https://reviews.llvm.org/D24419 llvm-svn: 290067
* Revert r289955 and r289962. This is causing lots of ASAN failures for us.Daniel Jasper2016-12-181-22/+10
| | | | | | | | Not sure whether it causes and ASAN false positive or whether it actually leads to incorrect code or whether it even exposes bad code. Hans, I'll get you instructions to reproduce this. llvm-svn: 290066
* [X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.Michael Zuckerman2016-12-181-3/+2
| | | | | | | | | | | | Commit on behalf of Gadi Haber Removed EVEX_V512 prefix from scalar EVEX instructions since HW ignores L'L bits anyway (LIG). 4 instructions are modified. The changed encodings are validated with XED. Rviewers: delena, igorb Differential revision: https://reviews.llvm.org/D27802 llvm-svn: 290065
* [X86][SSE] Add support for combining target shuffles to SHUFPS.Simon Pilgrim2016-12-181-2/+108
| | | | | | As discussed on D27692, the next step will be to allow cross-domain shuffles once the combined shuffle depth passes a certain point. llvm-svn: 290064
* [X86][SSE][AVX-512] Convert FAND/FOR/FXOR/FANDN nodes to integer operations ↵Craig Topper2016-12-181-13/+14
| | | | | | | | | | | | if they are available. This will allow a bunch of patterns to be removed. These nodes are only emitted for lowering FABS/FNEG/FNABS/FCOPYSIGN. Ideally we just wouldn't create these nodes if SSE2 or higher is available, but it was simple to just convert them in DAG combine. For SSE2, AVX, and AVX512 with DQI this is no functional change as the execution domain fixing pass ensures the right domain is selected regardless of the ISD opcode. For AVX-512 without DQI we end up using integer instructions since the floating point versions aren't available. But we were already doing that for any logical operations in code that didn't come from FABS/FNEG/FNABS/FCOPYSIGN so this seems no worse. And we get the benefit of being able to fold broadcasts now. llvm-svn: 290060
* [AVX-512] Use EVEX encoded XOR instruction for zeroing scalar registers when ↵Craig Topper2016-12-183-5/+22
| | | | | | | | DQI and VLX instructions are available. This can give the register allocator more registers to use. llvm-svn: 290057
* [AVX-512] Make sure VLX is also enabled before using EVEX encoded logic ops ↵Craig Topper2016-12-182-2/+2
| | | | | | for scalars. I missed this in r290049. llvm-svn: 290055
* [PDB] Don't reimplement CRC32David Majnemer2016-12-181-50/+5
| | | | | | | We already have a CRC32 implementation which is compatible with the PDB hash, reuse it. llvm-svn: 290054
* [PDB] Validate superblock addressesDavid Majnemer2016-12-181-0/+9
| | | | | | | - Validate the address of the block map. - Validate the address of the free block map. llvm-svn: 290053
* [AVX-512] Use EVEX encoded logic operations for scalar types when they are ↵Craig Topper2016-12-172-1/+38
| | | | | | available. This gives the register allocator more registers to work with. llvm-svn: 290049
* Revert "AArch64CollectLOH: Rewrite as block-local analysis."Matthias Braun2016-12-171-279/+841
| | | | | | | | It is still breaking Chrome. http://llvm.org/PR31361 This reverts commit r290026. llvm-svn: 290047
* [InstCombine] Simplify code slightly. NFCCraig Topper2016-12-171-1/+1
| | | | llvm-svn: 290046
* Revert "[libFuzzer] add an experimental flag -experimental_len_control=1 ↵Daniel Jasper2016-12-176-32/+9
| | | | | | | | | | | that sets max_len to 1M and tries to increases the actual max sizes of mutations very gradually. Also remove a bit of dead code" This reverts commit r289998. See comment: https://reviews.llvm.org/rL289998 llvm-svn: 290043
* [DWARF] - Introduce DWARFDebugPubTable class for dumping pub* sections.George Rimar2016-12-173-41/+77
| | | | | | | | | | Patch implements parser of pubnames/pubtypes tables instead of static function used before. It is now should be possible to reuse it in LLD or other projects and clean up the duplication code. Differential revision: https://reviews.llvm.org/D27851 llvm-svn: 290040
* [libFuzzer] use less memory for mergeKostya Serebryany2016-12-173-9/+13
| | | | llvm-svn: 290039
* Add custom type for PseudoSourceValueTom Stellard2016-12-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: PseudoSourceValue can be used to attach a target specific value for "well behaved" side-effects lowered from target specific intrinsics. This is useful whenever there is not an LLVM IR Value around when representing such "well behaved" side-effected operations in backends by attaching a MachineMemOperand with a custom PseudoSourceValue as this makes the scheduler not treating them as "GlobalMemoryObjects" which triggers a logic that makes the operation act like a barrier in the Schedule DAG. This patch adds another Kind to the PseudoSourceValue object which is "TargetCustom". It indicates a type of PseudoSourceValue that has a target specific meaning (aka. LLVM shouldn't assume any specific usage for such a PSV). It supports the possibility of having many different kinds of "TargetCustom" PseudoSourceValues. We had a discussion about if this was valuable or not (in particular because there was a believe that PSV were going away sooner or later) but seems like they are not going anywhere and I think they are useful backend side. It is not clear the interaction of this with MIRParser (do we need a target hook to parse these?) and I would like a comment from Alex about that :) Reviewers: arphaman, hfinkel, arsenm Subscribers: Eugene.Zelenko, llvm-commits Patch By: Marcello Maggioni Differential Revision: https://reviews.llvm.org/D13575 llvm-svn: 290037
* [libFuzzer] speed up __sanitizer_cov_trace_switch a bit more (remove DIV)Kostya Serebryany2016-12-171-1/+11
| | | | llvm-svn: 290034
* [libFuzzer] remove stale testKostya Serebryany2016-12-171-3/+0
| | | | llvm-svn: 290033
* [libFuzzer] when tracing switch statements, handle only one case at a time ↵Kostya Serebryany2016-12-173-6/+16
| | | | | | (to make things faster). Also ensure that the signals from value profile do not intersect with the regular coverage llvm-svn: 290031
* Revert "[GVNHoist] Move GVNHoist to function simplification part of pipeline."Evgeniy Stepanov2016-12-171-2/+2
| | | | | | | | This reverts r289696, which caused TSan perf regression. See PR31382. llvm-svn: 290030
* [Hexagon] Other attempt to fix build with enabled asserts broken in 290024 ↵Eugene Zelenko2016-12-171-0/+1
| | | | | | (NFC). llvm-svn: 290028
* [Hexagon] Fix build with enabled asserts broken in 290024 (NFC).Eugene Zelenko2016-12-171-0/+1
| | | | llvm-svn: 290027
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