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* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-021-38/+51
| | | | llvm-svn: 180959
* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-023-4/+20
| | | | llvm-svn: 180957
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-024-13/+45
| | | | llvm-svn: 180956
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-025-404/+305
| | | | llvm-svn: 180953
* [GV] Remove dead code which is really difficult to decipher.Shuxin Yang2013-05-021-26/+2
| | | | | | | | | | | Actually it took me couple of hours trying to make sense of them and only to find they are dead code. I guess the original author used "allSingleSucc" to indicate if there are any critial edge emanating from some blocks, and tried to perform code motion (actually speculation) in the presence of these critical edges; but later on he/she changed mind and decided to perform edge-splitting first. llvm-svn: 180951
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-022-0/+40
| | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. llvm-svn: 180946
* [mips] Fix the head Mips16RegisterInfo.cpp commentRichard Sandiford2013-05-021-2/+1
| | | | | | ...aka a test commit. llvm-svn: 180936
* Hexagon: Honor __builtin_expect by using branch probabilities.Jyotsna Verma2013-05-024-37/+122
| | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-023-447/+381
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> llvm-svn: 180921
* 80-col fixup.Michael Liao2013-05-021-2/+3
| | | | llvm-svn: 180915
* Avoid duplicating logic on frame register selecting when lowering eh_returnMichael Liao2013-05-021-9/+11
| | | | | | No functionality change llvm-svn: 180914
* Avoid duplicating logic on frame register selecting when lowering frameaddrMichael Liao2013-05-021-1/+3
| | | | | | No functionality change llvm-svn: 180912
* TiedTo flag can now be placed on implicit operands. isTwoAddrUse() should lookEvan Cheng2013-05-021-5/+3
| | | | | | | | | | | at all of the operands. Previously it was skipping over implicit operands which cause infinite looping when the two-address pass try to reschedule a two-address instruction below the kill of tied operand. I'm unable to come up with a reasonably sized test case. rdar://13747577 llvm-svn: 180906
* [mips] Rename class and functions. Simplify code.Akira Hatanaka2013-05-011-26/+29
| | | | | | No functionality changes. llvm-svn: 180897
* This exposes more MCJIT options via the C API:Filip Pizlo2013-05-013-32/+27
| | | | | | | | | | | | | | | | | | | | | CodeModel: It's now possible to create an MCJIT instance with any CodeModel you like. Previously it was only possible to create an MCJIT that used CodeModel::JITDefault. EnableFastISel: It's now possible to turn on the fast instruction selector. The CodeModel option required some trickery. The problem is that previously, we were ensuring future binary compatibility in the MCJITCompilerOptions by mandating that the user bzero's the options struct and passes the sizeof() that he saw; the bindings then bzero the remaining bits. This works great but assumes that the bitwise zero equivalent of any field is a sensible default value. But this is not the case for LLVMCodeModel, or its internal equivalent, llvm::CodeModel::Model. In both of those, the default for a JIT is CodeModel::JITDefault (or LLVMCodeModelJITDefault), which is not bitwise zero. Hence this change introduces LLVMInitializeMCJITCompilerOptions(), which will initialize the user's options struct with defaults. The user will use this in the same way that they would have previously used memset() or bzero(). MCJITCAPITest.cpp illustrates the change, as does the comment in ExecutionEngine.h. llvm-svn: 180893
* Revert r180737. The companion patch was reverted, and this is not relevant ↵Bill Wendling2013-05-011-15/+0
| | | | | | right now. llvm-svn: 180889
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-0114-263/+336
| | | | llvm-svn: 180885
* Hexagon: Clear isKill flag on the predicate register inJyotsna Verma2013-05-011-1/+5
| | | | | | PredicateInstruction function. llvm-svn: 180884
* This patch breaks up Wrap.h so that it does not have to include all of Filip Pizlo2013-05-0119-19/+15
| | | | | | | | | | | | | | | | | | | | | | | | the things, and renames it to CBindingWrapping.h. I also moved CBindingWrapping.h into Support/. This new file just contains the macros for defining different wrap/unwrap methods. The calls to those macros, as well as any custom wrap/unwrap definitions (like for array of Values for example), are put into corresponding C++ headers. Doing this required some #include surgery, since some .cpp files relied on the fact that including Wrap.h implicitly caused the inclusion of a bunch of other things. This also now means that the C++ headers will include their corresponding C API headers; for example Value.h must include llvm-c/Core.h. I think this is harmless, since the C API headers contain just external function declarations and some C types, so I don't believe there should be any nasty dependency issues here. llvm-svn: 180881
* SROA: Generate selects instead of shuffles when blending values because this ↵Nadav Rotem2013-05-011-8/+6
| | | | | | | | is the cannonical form. Shuffles are more difficult to lower and we usually don't touch them, while we do optimize selects more often. llvm-svn: 180875
* [inline asm] Return an undef SDValue of the expected value type, rather thanChad Rosier2013-05-011-1/+1
| | | | | | | | | report a fatal error. This allows us to continue processing the translation unit. Test case to come on the clang side because we need an inline asm diagnostics handler in place. rdar://13446483 llvm-svn: 180873
* Optimize away nop CONCAT_VECTOR nodes.Nadav Rotem2013-05-011-0/+39
| | | | | | | | | Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector. rdar://13402653 PR15866 llvm-svn: 180871
* Now that the underlying issue is fixed, revert r180750 and r180722.Rafael Espindola2013-05-013-13/+24
| | | | | | | | | | | The cause of the windows failures was fixed by r180791. Revert to the state after Sabre's original revert. Original message: revert r179735, it has no testcases, and doesn't really make sense. llvm-svn: 180844
* Put VMOVPQIto64rr in the VRPDI class.Rafael Espindola2013-05-011-3/+3
| | | | | | Patch by Joshua Magee. llvm-svn: 180842
* Fixes a buffer overrun where the allocated buffer wasn't large enough to ↵Aaron Ballman2013-05-011-1/+8
| | | | | | accommodate the closing quote escape rules in some instances. llvm-svn: 180836
* Revert "InstCombine: Fold more shuffles of shuffles."Jim Grosbach2013-05-011-12/+5
| | | | | | | | | This reverts commit r180802 There's ongoing discussion about whether this is the right place to make this transformation. Reverting for now while we figure it out. llvm-svn: 180834
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-307-37/+43
| | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. llvm-svn: 180827
* Only pass 'returned' to target-specific lowering code when the value of ↵Stephen Lin2013-04-302-28/+42
| | | | | | entire register is guaranteed to be preserved. llvm-svn: 180825
* Fix a use after free. RI is freed before the call to getDebugLoc(). ToRichard Trieu2013-04-301-4/+5
| | | | | | prevent this, capture the location before RI is freed. llvm-svn: 180824
* [mips] Instruction selection patterns for DSP-ASE vector select and compareAkira Hatanaka2013-04-305-3/+145
| | | | | | instructions. llvm-svn: 180820
* Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl2013-04-307-58/+36
| | | | | | | | | | can express a" because it breaks some buildbots. This reverts commit 180816. llvm-svn: 180819
* Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl2013-04-307-36/+58
| | | | | | | | | | | | register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 llvm-svn: 180816
* MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.Andrew Trick2013-04-301-0/+6
| | | | | | I'll fix the heuristic in a general way in a follow-up commit. llvm-svn: 180815
* [mips] Simplify code.Akira Hatanaka2013-04-301-4/+1
| | | | | | No intended functionality changes. llvm-svn: 180807
* Fix a typoNadav Rotem2013-04-301-1/+1
| | | | llvm-svn: 180806
* InstCombine: Fold more shuffles of shuffles.Jim Grosbach2013-04-301-5/+12
| | | | | | | | | | | Always fold a shuffle-of-shuffle into a single shuffle when there's only one input vector in the first place. Continue to be more conservative when there's multiple inputs. rdar://13402653 PR15866 llvm-svn: 180802
* [mips] Clear isCommutable bit of instructions which are not commutable.Akira Hatanaka2013-04-301-14/+8
| | | | llvm-svn: 180801
* LocalStackSlotAllocation improvementsHal Finkel2013-04-301-94/+111
| | | | | | | | | | | | First, taking advantage of the fact that the virtual base registers are allocated in order of the local frame offsets, remove the quadratic register-searching behavior. Because of the ordering, we only need to check the last virtual base register created. Second, store the frame index in the FrameRef structure, and get the frame index and the local offset from this structure at the top of the loop iteration. This allows us to de-nest the loops in insertFrameReferenceRegisters (and I think makes the code cleaner). I also moved the needsFrameBaseReg check into the first loop over instructions so that we don't bother pushing FrameRefs for instructions that don't want a virtual base register anyway. Lastly, and this is the only functionality change, avoid the creation of single-use virtual base registers. These are currently not useful because, in general, they end up replacing what would be one r+r instruction with an add and a r+i instruction. Committing this removes the XFAIL in CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll Jim has okayed this off-list. llvm-svn: 180799
* Text files should not be marked executable.Rafael Espindola2013-04-301-0/+0
| | | | | | Patch by Oliver Pinter. llvm-svn: 180797
* Spelling. Thanks, Eric.Adrian Prantl2013-04-301-1/+1
| | | | llvm-svn: 180794
* Set debug locations for branch instructions created during inlining, evenAdrian Prantl2013-04-301-2/+10
| | | | | | | | the inlined function has multiple returns. rdar://problem/12415623 llvm-svn: 180793
* Change getSlotIndex to return unsigned.Rafael Espindola2013-04-302-4/+4
| | | | | | | | | | | The actual storage was already using unsigned, but the interface was using uint64_t. This is wasteful on 32 bits and looks to be the root causes of a miscompilation on Windows where a value was being sign extended to 64bits to compare with the result of getSlotIndex. Patch by Pasi Parviainen! llvm-svn: 180791
* Fix Addend computation for non external relocations on Macho.Rafael Espindola2013-04-302-28/+20
| | | | llvm-svn: 180790
* Fix a bug in foldSelectICmpAndOr.David Majnemer2013-04-301-1/+2
| | | | | | | Differences in bitwidth between X and Y could exist even if C1 and C2 have the same Log2 representation. llvm-svn: 180779
* s tightens up the encoding description for ARM post-indexed ldr ↵Mihai Popa2013-04-301-0/+1
| | | | | | instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. llvm-svn: 180778
* Fix "Combine bit test + conditional or into simple math"David Majnemer2013-04-301-0/+64
| | | | | | | | | This fixes the optimization introduced in r179748 and reverted in r179750. While the optimization was sound, it did not properly respect differences in bit-width. llvm-svn: 180777
* Refactoring patch.Stepan Dyatkovskiy2013-04-305-66/+100
| | | | | | | | | | | | 1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong. This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method. 2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed. 3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons. llvm-svn: 180774
* Collect the Addend for external relocs.Rafael Espindola2013-04-301-5/+12
| | | | | | | This fixes 2013-04-04-RelocAddend.ll. We don't have a testcase for non external relocs with an Addend. I will try to write one. llvm-svn: 180767
* R600: Always use texture cache for compute shadersVincent Lejeune2013-04-301-2/+6
| | | | | | This will improve the performance of memory reads. llvm-svn: 180762
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