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* Implement 64-bit support for thread local storage handling.Akira Hatanaka2011-12-085-55/+51
| | | | | | | | | | - Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. llvm-svn: 146175
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-084-10/+79
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* ARM assembler support for register name aliases.Jim Grosbach2011-12-081-2/+16
| | | | | | rdar://10550084 llvm-svn: 146170
* Make MachineInstr instruction property queries more flexible. This change allEvan Cheng2011-12-081-5/+5
| | | | | | | | clients to decide whether to look inside bundled instructions and whether the query should return true if any / all bundled instructions have the queried property. llvm-svn: 146168
* Many of the SSE patterns should not be selected when AVX is available. This ↵Evan Cheng2011-12-084-4/+11
| | | | | | | | | | | | | | | | | | led to the following code in X86Subtarget.cpp if (HasAVX) X86SSELevel = NoMMXSSE; This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected. However, this breaks instructions which do not have AVX variants. The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX(). Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change. However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case, the prefetch instructions. rdar://10538297 llvm-svn: 146163
* Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsicsDaniel Dunbar2011-12-081-22/+0
| | | | | | | sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).", it is failing tests. llvm-svn: 146157
* Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this ↵Jan Sjödin2011-12-082-14/+11
| | | | | | and fix the encoding. llvm-svn: 146151
* Fix a bug in the integer-promotion of bitcast operations on vector types.Nadav Rotem2011-12-081-1/+1
| | | | | | | We must not issue a bitcast operation for integer-promotion of vector types, because the location of the values in the vector may be different. llvm-svn: 146150
* Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-081-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). llvm-svn: 146143
* MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR ↵Hal Finkel2011-12-081-1/+1
| | | | | | (another find by -verify-machineinstrs) llvm-svn: 146137
* Reverting r145899 as it breaks clang self-hostingPete Cooper2011-12-081-0/+66
| | | | llvm-svn: 146136
* ARM NEON two-operand aliases for VSHL(immediate).Jim Grosbach2011-12-083-0/+35
| | | | llvm-svn: 146125
* Drop the HasInlineAsm flag.Jakob Stoklund Olesen2011-12-081-8/+2
| | | | | | | | | | It is not used any more. We are tracking inline assembly misalignments directly through the BBInfo.Unalign and KnownBits fields. A simple conservative size estimate is not good enough since it can cause alignment padding to be underestimated. llvm-svn: 146124
* ARM NEON two-operand aliases for VSHL(register).Jim Grosbach2011-12-081-0/+35
| | | | llvm-svn: 146123
* Simplify offset verification.Jakob Stoklund Olesen2011-12-081-9/+4
| | | | llvm-svn: 146121
* Fix copy/past-o.Jim Grosbach2011-12-081-2/+2
| | | | llvm-svn: 146120
* ARM NEON two-operand aliases for VMUL.Jim Grosbach2011-12-081-0/+5
| | | | llvm-svn: 146119
* Don't include alignment padding in BBInfo.Size.Jakob Stoklund Olesen2011-12-081-145/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | Compute alignment padding before and after basic blocks dynamically. Heed basic block alignment. This simplifies bookkeeping because we don't have to constantly add and remove padding from BBInfo.Size. It also makes it possible to track the extra known alignment bits we get after a tBR_JTr terminator and when entering an aligned basic block. This makes the ARMConstantIslandPass aware of aligned basic blocks. It is tricky to model block alignment correctly when dealing with inline assembly and tBR_JTr instructions that have variable size. If inline assembly turns out to be smaller than expected, that may cause following alignment padding to be larger than expected. This could cause constant pool entries to move out of range. To avoid that problem, we use the worst case alignment padding following inline assembly. This may cause slightly suboptimal constant island placement in aligned basic blocks following inline assembly. Normal functions should be unaffected. llvm-svn: 146118
* ARM VFP support 'fmrs/fmsr' aliases for 'vldr'Jim Grosbach2011-12-082-0/+3
| | | | llvm-svn: 146116
* ARM VFP support 'flds/fldd' aliases for 'vldr'Jim Grosbach2011-12-082-1/+7
| | | | llvm-svn: 146115
* ARM optional destination operand variants for VEXT instructions.Jim Grosbach2011-12-081-0/+17
| | | | llvm-svn: 146114
* Fix 80-column.Chad Rosier2011-12-081-10/+11
| | | | | | Simplify code. llvm-svn: 146112
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-083-10/+56
| | | | llvm-svn: 146111
* Fix comments.Chad Rosier2011-12-081-0/+1
| | | | llvm-svn: 146109
* EngineBuilder: support for custom TargetOptions. Fixes thePeter Collingbourne2011-12-072-2/+5
| | | | | | ExceptionDemo example. llvm-svn: 146108
* Fix comments.Chad Rosier2011-12-071-2/+2
| | | | llvm-svn: 146107
* ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.Jim Grosbach2011-12-071-1/+3
| | | | | | For 'gas' compatibility. llvm-svn: 146106
* Modify class ReadHardware and add definition of 64-bit version of instructionAkira Hatanaka2011-12-072-3/+6
| | | | | | RDHWR. llvm-svn: 146101
* Add newline.Akira Hatanaka2011-12-071-1/+2
| | | | llvm-svn: 146100
* Add 64-bit HWR29 register.Akira Hatanaka2011-12-071-0/+2
| | | | llvm-svn: 146099
* 32 to 64-bit anyext pattern.Akira Hatanaka2011-12-071-0/+4
| | | | llvm-svn: 146097
* 32 to 64-bit zext pattern.Akira Hatanaka2011-12-071-0/+5
| | | | llvm-svn: 146096
* ARM two-operand aliases for VAND/VEOR/VORR instructions.Jim Grosbach2011-12-071-0/+26
| | | | llvm-svn: 146095
* ARM two-operand aliases for VADDW instructions.Jim Grosbach2011-12-071-0/+14
| | | | llvm-svn: 146093
* ARM two-operand aliases for VADD instructions.Jim Grosbach2011-12-071-0/+24
| | | | llvm-svn: 146091
* Flesh out a bit more of the bitcode use-list ordering preservation code.Chad Rosier2011-12-071-5/+87
| | | | | | | Nothing too interesting at this point, but comments are welcome. Part of rdar://9860654 and PR5680. llvm-svn: 146090
* Variable cleanup. Based on past patch submittals variable names haveBruno Cardoso Lopes2011-12-072-55/+60
| | | | | | | been normalized and more descriptive comments added. Patch by Reed Kotler and Jack Carter. llvm-svn: 146088
* Make sure we correctly set LiveRegGens when a call is unscheduled. ↵Eli Friedman2011-12-071-1/+8
| | | | | | <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling. llvm-svn: 146087
* 64-bit WrapperPICPat patterns.Akira Hatanaka2011-12-071-0/+6
| | | | llvm-svn: 146086
* Fix an assertion in the scheduler. PR11386. No testcase included because ↵Eli Friedman2011-12-071-3/+2
| | | | | | it's rather delicate. llvm-svn: 146083
* Define base class for WrapperPICPat.Akira Hatanaka2011-12-071-7/+7
| | | | llvm-svn: 146081
* Modify LowerFCOPYSIGN to handle Mips64.Akira Hatanaka2011-12-071-14/+22
| | | | llvm-svn: 146080
* Begin adding experimental support for preserving use-list ordering of bitcodeChad Rosier2011-12-073-0/+78
| | | | | | | | | | files. First, add a new block USELIST_BLOCK to the bitcode format. This is where USELIST_CODE_ENTRYs will be stored. The format of the USELIST_CODE_ENTRYs have not yet been defined. Add support in the BitcodeReader for parsing the USELIST_BLOCK. Part of rdar://9860654 and PR5680. llvm-svn: 146078
* These global variables aren't thread-safe, STATISTIC is. Andy Trick tells meNick Lewycky2011-12-071-66/+12
| | | | | | that he isn't using these any more, so just delete them. llvm-svn: 146076
* ValueEnumerator - debug dump().Chad Rosier2011-12-072-1/+43
| | | | llvm-svn: 146070
* Fix comment.Akira Hatanaka2011-12-071-2/+1
| | | | llvm-svn: 146063
* Fix comment.Akira Hatanaka2011-12-071-1/+1
| | | | llvm-svn: 146062
* Fix 64-bit immediate patterns.Akira Hatanaka2011-12-073-6/+25
| | | | llvm-svn: 146059
* Nuke inadvertant debugging commit.Jim Grosbach2011-12-071-3/+0
| | | | llvm-svn: 146057
* Darwin assembler improved relocs when w/o subsections_via_symbols.Jim Grosbach2011-12-072-1/+9
| | | | | | | | When the file isn't being built with subsections-via-symbols, symbol differences involving non-local symbols can be resolved more aggressively. Needed for gas compatibility. llvm-svn: 146054
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