summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-1014-16/+12
| | | | llvm-svn: 205961
* YAMLIO: Allow scalars to dictate quotation rulesDavid Majnemer2014-04-102-10/+6
| | | | | | | Introduce ScalarTraits::mustQuote which determines whether or not a StringRef needs quoting before it is acceptable to output. llvm-svn: 205955
* Use range-based for loops. No functionality change.Simon Atanasyan2014-04-101-25/+16
| | | | llvm-svn: 205953
* Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid).NAKAMURA Takumi2014-04-101-4/+4
| | | | | FIXME: Could we use SmallString here? llvm-svn: 205950
* ARM64: add an explicit cast to silence a silly warningSaleem Abdulrasool2014-04-101-2/+4
| | | | | | | | | | GCC 4.8 complains with: warning: enumeral and non-enumeral type in conditional expression Although this is silly and harmless in this case, add an explicit cast to silence the warning. llvm-svn: 205949
* [ARM64] Fix immediate cost calculation for types larger than i64.Juergen Ributzka2014-04-101-1/+1
| | | | | | | | | | The immediate cost calculation code was hitting an assertion in the included test case, because APInt was still internally 128-bits. Truncating it to 64-bits fixed the issue. Fixes <rdar://problem/16572521>. llvm-svn: 205947
* Revert "For the ARM integrated assembler add checking of the alignments on ↵Reid Kleckner2014-04-103-894/+432
| | | | | | | | | | | | | vld/vst instructions. And report errors for alignments that are not supported." It doesn't build with MSVC 2012, because MSVC doesn't allow union members that have non-trivial default constructors. This change added 'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor non-trivial. This reverts commit r205930. llvm-svn: 205944
* Fix to support properly cleaning up failed address sinking against constantsJim Grosbach2014-04-101-2/+3
| | | | | | | | | | | As it turns out the source of the sunkaddr can be a constant, in which case there is not an instruction to delete, causing the cleanup code introduced in r204833 to crash. This patch adds a dynamic check to ensure the deleted value is in fact an instruction and not a constant. Patch by Louis Gerbarg <lgg@apple.com> llvm-svn: 205941
* Add support for load folding of avx1 logical instructionsJim Grosbach2014-04-091-0/+13
| | | | | | | | | | | | | | | | | | AVX supports logical operations using an operand from memory. Unfortunately because integer operations were not added until AVX2 the AVX1 logical operation's types were preventing the isel from folding the loads. In a limited number of cases the peephole optimizer would fold the loads, but most were missed. This patch adds explicit patterns with appropriate casts in order for these loads to be folded. The included test cases run on reduced examples and disable the peephole optimizer to ensure the folds are being pattern matched. Patch by Louis Gerbarg <lgg@apple.com> rdar://16355124 llvm-svn: 205938
* SelectionDAG: Don't constant fold target-specific nodes.Jim Grosbach2014-04-091-0/+6
| | | | | | | | | | | | | | FoldConstantArithmetic() only knows how to deal with a few target independent ISD opcodes. Bail early if it sees a target-specific ISD node. These node do funny things with operand types which may break the assumptions of the code that follows, and there's no actual folding that can be done anyway. For example, non-constant 256 bit vector shifts on X86 have a shift-amount operand that's a 128-bit v4i32 vector regardless of what the first operand type is and that breaks the assumption that the operand types must match. rdar://16530923 llvm-svn: 205937
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-093-432/+894
| | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. rdar://11312406 llvm-svn: 205930
* [AArch64] Implement the isZExtFree APIs.Chad Rosier2014-04-092-0/+40
| | | | llvm-svn: 205926
* [AArch64] Implement the isTruncateFree API.Chad Rosier2014-04-092-0/+25
| | | | | | | | | In AArch64 i64 to i32 truncate operation is a subregister access. This allows more opportunities for LSR optmization to eliminate variables of different types (i32 and i64). llvm-svn: 205925
* [DAGCombiner] DAG combine does not know how to combine indexed loads withQuentin Colombet2014-04-091-2/+5
| | | | | | | | | | | sign/zero/any extensions. However a few places were not checking properly the property of the load and were turning an indexed load into a regular extended load. Therefore the indexed value was lost during the process and this was triggering an assertion. <rdar://problem/16389332> llvm-svn: 205923
* Simple fix for build failures resulting from r205867.Bob Wilson2014-04-091-1/+1
| | | | llvm-svn: 205918
* Revert "Revert "YAMLIO: Encode ambiguous hex strings explicitly""David Majnemer2014-04-091-1/+2
| | | | | | | | | Don't quote octal compatible strings if they are only two wide, they aren't ambiguous. This reverts commit r205857 which reverted r205857. llvm-svn: 205914
* obj2yaml: Don't crash if the characteristics field is zeroDavid Majnemer2014-04-091-0/+1
| | | | | | | | | obj2yaml would fail when seeing a Weak External auxiliary record with a characteristics field holding zero instead of one of IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY, IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY, or IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY. llvm-svn: 205911
* [NVPTX] Add preliminary intrinsics and codegen support for textures/surfacesJustin Holewinski2014-04-0914-20/+3855
| | | | | | This commit adds intrinsics and codegen support for the surface read/write and texture read instructions that take an explicit sampler parameter. Codegen operates on image handles at the PTX level, but falls back to direct replacement of handles with kernel arguments if image handles are not enabled. Note that image handles are explicitly disabled for all target architectures in this change (to be enabled later). llvm-svn: 205907
* [NVPTX] Add support for addrspacecast in global variable initializers, ↵Justin Holewinski2014-04-092-4/+69
| | | | | | including emitting generic() when casting to address space 0. llvm-svn: 205906
* [NVPTX] Add query support for read-write images and managed variablesJustin Holewinski2014-04-094-3/+52
| | | | | | This also fixes a bug in the annotation cache where the cache will not be cleared between modules if multiple modules are compiled in the same process. llvm-svn: 205905
* Fix some doc and comment typosAlp Toker2014-04-0911-17/+17
| | | | llvm-svn: 205899
* [ARM64] Change SYS without a register to an alias to make disassembling more ↵Bradley Smith2014-04-093-22/+10
| | | | | | consistant. llvm-svn: 205898
* [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith2014-04-091-1/+6
| | | | llvm-svn: 205897
* [ARM64] Properly support both apple and standard syntax for FMOVBradley Smith2014-04-091-11/+10
| | | | llvm-svn: 205896
* [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2014-04-091-4/+14
| | | | llvm-svn: 205895
* [ARM64] Conditional branches must always print their condition code, even AL.Bradley Smith2014-04-091-2/+1
| | | | llvm-svn: 205894
* [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205893
* [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.Bradley Smith2014-04-094-13/+67
| | | | llvm-svn: 205892
* [ARM64] Add missing shifted register MVN alias to ORNBradley Smith2014-04-092-0/+13
| | | | llvm-svn: 205891
* [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith2014-04-091-1/+3
| | | | llvm-svn: 205890
* [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ↵Bradley Smith2014-04-093-19/+93
| | | | | | dumb alias. llvm-svn: 205889
* [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all ↵Bradley Smith2014-04-092-41/+68
| | | | | | labels types llvm-svn: 205888
* [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205887
* [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW ↵Bradley Smith2014-04-091-2/+4
| | | | | | should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. llvm-svn: 205886
* [ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith2014-04-092-2/+2
| | | | llvm-svn: 205885
* [ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith2014-04-092-2/+2
| | | | llvm-svn: 205884
* [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ↵Bradley Smith2014-04-092-1/+15
| | | | | | zero but should be decoded/disassembled with any value. llvm-svn: 205883
* [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith2014-04-092-8/+24
| | | | llvm-svn: 205882
* [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have ↵Bradley Smith2014-04-091-1/+5
| | | | | | the top bit of their immediate clear. llvm-svn: 205881
* [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.Bradley Smith2014-04-091-1/+1
| | | | llvm-svn: 205880
* [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.Bradley Smith2014-04-091-0/+6
| | | | llvm-svn: 205879
* [ARM64] Floating point to fixed point scaled conversions are only available ↵Bradley Smith2014-04-092-14/+22
| | | | | | on fcvtzs and fcvtzu. llvm-svn: 205878
* [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith2014-04-092-1/+18
| | | | llvm-svn: 205877
* [ARM64] Add missing tlbi operands and error for extra/missing register on ↵Bradley Smith2014-04-092-0/+32
| | | | | | tlbi aliases. llvm-svn: 205876
* [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.Bradley Smith2014-04-092-141/+74
| | | | llvm-svn: 205875
* [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ↵Bradley Smith2014-04-092-4/+32
| | | | | | stores, so the unused register fields are set to all-ones canonically but are recognised with any value. llvm-svn: 205874
* [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated ↵Bradley Smith2014-04-091-2/+7
| | | | | | during disassembly. llvm-svn: 205873
* [ARM64] Remove PrefetchOp and use ARM64PRFM instead.Bradley Smith2014-04-093-81/+14
| | | | llvm-svn: 205872
* [ARM64] Add WZR to isGPR32Register, since every use needs to check for this ↵Bradley Smith2014-04-091-4/+3
| | | | | | anyway. llvm-svn: 205871
* [ARM64] Remove ARM64SYS.Bradley Smith2014-04-091-665/+0
| | | | llvm-svn: 205870
OpenPOWER on IntegriCloud