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* Remove some unsupported-feature comments from PPC.tdHal Finkel2013-04-031-3/+0
| | | | | | These refer to the reciprocal estimate support recently committed. llvm-svn: 178618
* Use PPC reciprocal estimates with Newton iteration in fast-math modeHal Finkel2013-04-037-30/+321
| | | | | | | | | | | | | | | | | | | When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. llvm-svn: 178617
* Fix the fde encoding used by mips to match gas.Rafael Espindola2013-04-031-4/+7
| | | | | | | | | | | | | This finally fixes the encoding. The patch also * Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking the wrong value. * Merge fde-reloc.s and eh-frame.s into a single test, since the only difference was the run lines. * Don't blindly test the content of the entire .eh_frame section. It makes it hard to anyone actually fixing a bug and hitting a difference in a binary blob. Instead, use a CHECK for each field and document what is being checked. llvm-svn: 178615
* Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that ↵Aaron Ballman2013-04-031-23/+2
| | | | | | doesn't understand the xgetbv instruction for some reason. Will revisit when time permits. llvm-svn: 178614
* Remove an optimization where we were changing an objc_autorelease into an ↵Michael Gottesman2013-04-031-16/+1
| | | | | | | | | | | | | | | | | | | | | objc_autoreleaseReturnValue. The semantics of ARC implies that a pointer passed into an objc_autorelease must live until some point (potentially down the stack) where an autorelease pool is popped. On the other hand, an objc_autoreleaseReturnValue just signifies that the object must live until the end of the given function at least. Thus objc_autorelease is stronger than objc_autoreleaseReturnValue in terms of the semantics of ARC* implying that performing the given strength reduction without any knowledge of how this relates to the autorelease pool pop that is further up the stack violates the semantics of ARC. *Even though objc_autoreleaseReturnValue if you know that no RV optimization will occur is more computationally expensive. llvm-svn: 178612
* Improved comment. No functionality change.Michael Gottesman2013-04-031-1/+2
| | | | llvm-svn: 178605
* Attempting to fix the build on older GCC versions.Aaron Ballman2013-04-031-1/+2
| | | | llvm-svn: 178604
* This patch addresses PR15351 by explicitly checking for AVX supportAaron Ballman2013-04-031-2/+22
| | | | | | when getting the host processor information. llvm-svn: 178598
* Formatting.Eric Christopher2013-04-021-2/+1
| | | | llvm-svn: 178589
* [mips] Small update to the implementation of eh.return for Mips.Akira Hatanaka2013-04-021-0/+4
| | | | | | | | | | This patch initializes t9 to the handler address, but only if the relocation model is pic. This handles the case where handler to which eh.return jumps points to the start of the function. Patch by Sasa Stankovic. llvm-svn: 178588
* Support and test template arguments for unions.Eric Christopher2013-04-021-1/+2
| | | | llvm-svn: 178586
* Reformat arguments.Eric Christopher2013-04-021-4/+6
| | | | llvm-svn: 178585
* [mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.Akira Hatanaka2013-04-021-0/+36
| | | | | | | | | | This patch fixes the following two tests which have been failing on llvm-mips-linux builder since r178403: LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll LLVM :: Analysis/Profiling/load-branch-weights-loops.ll llvm-svn: 178584
* Allow MachineTraceMetrics to be used when the model has no resources.Jakob Stoklund Olesen2013-04-022-7/+11
| | | | | | | It it still possible to extract information from itineraries, for example. llvm-svn: 178582
* [ms-inline asm] Add support for parsing variables with namespace aliasChad Rosier2013-04-021-0/+54
| | | | | | | | | | | | | qualifiers. This patch only adds support for parsing these identifiers in the X86AsmParser. The front-end interface isn't capable of looking up these identifiers at this point in time. The end result is the compiler now errors during object file emission, rather than at parse time. Test case coming shortly. Part of rdar://13499009 and PR13340 llvm-svn: 178566
* Fix PR15630: Replace faulty stdcx. with stwcx.Bill Schmidt2013-04-021-1/+1
| | | | | | | | | | When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. llvm-svn: 178559
* Don't attempt MTM heuristics without a scheduling model present.Jakob Stoklund Olesen2013-04-021-0/+4
| | | | | | This should fix the PPC buildbots. llvm-svn: 178558
* Count processor resources individually in MachineTraceMetrics.Jakob Stoklund Olesen2013-04-021-9/+144
| | | | | | | | | | | | | | | The new instruction scheduling models provide information about the number of cycles consumed on each processor resource. This makes it possible to estimate ILP more accurately than simply counting instructions / issue width. The functions getResourceDepth() and getResourceLength() now identify the limiting processor resource, and return a cycle count based on that. This gives more precise resource information, particularly in traces that use one resource a lot more than others. llvm-svn: 178553
* [fast-isel] Use the correct API to disable FastLowerArguments for Win64.Chad Rosier2013-04-021-1/+1
| | | | llvm-svn: 178549
* DAGCombiner: Merge store/loads when we have extload/truncstoresArnold Schwaighofer2013-04-021-0/+19
| | | | | | | | | | | | | | | | This is helps on architectures where i8,i16 are not legal but we have byte, and short loads/stores. Allowing us to merge copies like the one below on ARM. copy(char *a, char *b, int n) { do { int t0 = a[0]; int t1 = a[1]; b[0] = t0; b[1] = t1; radar://13536387 llvm-svn: 178546
* [NVPTX] Fix a few style issues in NVVMReflectJustin Holewinski2013-04-021-72/+56
| | | | llvm-svn: 178536
* Use a worklist to avoid a sneaky iterator invalidation.Bill Wendling2013-04-021-3/+3
| | | | | | | | | | | | | The iterator could be invalidated when it's recursively deleting a whole bunch of constant expressions in a constant initializer. Note: This was only reproducible if `opt' was run on a `.bc' file. If `opt' was run on a `.ll' file, it wouldn't crash. This is why the test first pushes the `.ll' file through `llvm-as' before feeding it to `opt'. PR15440 llvm-svn: 178531
* Add 64-bit load and store instructions.Jakob Stoklund Olesen2013-04-021-0/+68
| | | | | | There is only a few new instructions, the rest is handled with patterns. llvm-svn: 178528
* Basic 64-bit ALU operations.Jakob Stoklund Olesen2013-04-021-0/+38
| | | | | | | SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. llvm-svn: 178527
* Materialize 64-bit immediates.Jakob Stoklund Olesen2013-04-021-0/+88
| | | | | | | The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. llvm-svn: 178526
* Add 64-bit shift instructions.Jakob Stoklund Olesen2013-04-023-0/+86
| | | | | | | | | | | SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. llvm-svn: 178525
* Add predicates for distinguishing 32-bit and 64-bit modes.Jakob Stoklund Olesen2013-04-021-0/+6
| | | | | | | | | | | The 'sparc' architecture produces 32-bit code while 'sparcv9' produces 64-bit code. It is also possible to run 32-bit code using SPARC v9 instructions with: llc -march=sparc -mattr=+v9 llvm-svn: 178524
* Add support for 64-bit calling convention.Jakob Stoklund Olesen2013-04-023-11/+115
| | | | | | | | | | | | This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. llvm-svn: 178523
* Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen2013-04-026-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. llvm-svn: 178522
* Fix typo in PPCISelLoweringHal Finkel2013-04-021-1/+1
| | | | | | Thanks to Bill Schmidt for finding this in review of r178480. llvm-svn: 178521
* The divide unit is not pipeline, but it is still buffered.Andrew Trick2013-04-022-4/+4
| | | | | | | | | | | | | | | | | | | | Buffered means a later divide may be executed out-of-order while a prior divide is sitting (buffered) in a reservation station. You can tell it's not pipelined, because operations that use it reserve it for more than one cycle: def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { let Latency = 25; let ResourceCycles = [1, 10]; } We don't currently distinguish between an unpipeline operation and one that is split into multiple micro-ops requiring the same unit. Except that the later may have NumMicroOps > 1 if they also consume issue/dispatch resources. llvm-svn: 178519
* Target/R600: Fix CMake build to add missing files.NAKAMURA Takumi2013-04-011-0/+3
| | | | llvm-svn: 178508
* Mips direct object exception handling regressionJack Carter2013-04-011-3/+4
| | | | | | | | | | | | | | | | | Revision 177141 caused a regression in all but mips64 little endian. That is because none of the other Mips targets had test cases checking the contents of the .eh_frame section. This patch fixes both the llvm code and adds an assembler test case to include the current 4 flavors. The test cases unfortunately rely on llvm-objdump. A preferable method would be to use a pretty printer output such as what readelf -wf <elf_file> would give. I also changed the name of the test case to correct a typo. llvm-svn: 178506
* R600: Add support for native control flowVincent Lejeune2013-04-015-1/+386
| | | | llvm-svn: 178505
* R600/SI: Share code recording ShaderTypeAttribute between generationsVincent Lejeune2013-04-016-28/+60
| | | | llvm-svn: 178504
* R600: Emit CF_ALU and use true kcache register.Vincent Lejeune2013-04-016-10/+397
| | | | llvm-svn: 178503
* Fix top-comment header and some indentationEli Bendersky2013-04-012-3/+3
| | | | llvm-svn: 178492
* Fix a bad assert in PPCTargetLoweringHal Finkel2013-04-011-2/+2
| | | | llvm-svn: 178489
* Correct assertion conditionShuxin Yang2013-04-011-1/+1
| | | | llvm-svn: 178484
* Merge load/store sequences with adresses: base + index + offsetArnold Schwaighofer2013-04-011-25/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We would also like to merge sequences that involve a variable index like in the example below. int index = *idx++ int i0 = c[index+0]; int i1 = c[index+1]; b[0] = i0; b[1] = i1; By extending the parsing of the base pointer to handle dags that contain a base, index, and offset we can handle examples like the one above. The dag for the code above will look something like: (load (i64 add (i64 copyfromreg %c) (i64 signextend (i8 load %index)))) (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) The code that parses the tree ignores the intermediate sign extensions. However, if there is a sign extension it needs to be on all indexes. (load (i64 add (i64 copyfromreg %c) (i64 signextend (add (i8 load %index) (i8 1)))) vs (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) radar://13536387 llvm-svn: 178483
* Add more PPC floating-point conversion instructionsHal Finkel2013-04-017-33/+134
| | | | | | | | | The P7 and A2 have additional floating-point conversion instructions which allow a direct two-instruction sequence (plus load/store) to convert from all combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores, only some combinations were directly available). llvm-svn: 178480
* Use ImmToIdxMap.count in PPCRegisterInfoHal Finkel2013-04-011-2/+1
| | | | | | | Code improvement suggested by Jakob (in review of r178450). No functionality change intended. llvm-svn: 178473
* Add the PPC popcntw instructionHal Finkel2013-04-012-1/+8
| | | | | | | | | The popcntw instruction is available whenever the popcntd instruction is available, and performs a separate popcnt on the lower and upper 32-bits. Ignoring the high-order count, this can be used for the 32-bit input case (saving on the explicit zero extension otherwise required to use popcntd). llvm-svn: 178470
* Add support for vector data types in the LLVM interpreter.Nadav Rotem2013-04-013-3/+182
| | | | | | | Patch by: Veselov, Yuri <Yuri.Veselov@intel.com> llvm-svn: 178469
* Treat PPCISD::STFIWX like the memory opcode that it isHal Finkel2013-04-012-6/+13
| | | | | | | | | | | PPCISD::STFIWX is really a memory opcode, and so it should come after FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create nodes using it. No functionality change intended (although there could be optimization benefits from preserving the MMO information). llvm-svn: 178468
* Remove unused typedef.Duncan Sands2013-04-011-1/+0
| | | | llvm-svn: 178462
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-04-014-41/+85
| | | | | | | | | | | | | Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
* X86TTI: Add accurate costs for itofp operations, based on the actual ↵Benjamin Kramer2013-04-011-4/+27
| | | | | | instruction counts. llvm-svn: 178459
* Whitespace cleanupJoe Abbey2013-04-012-2/+2
| | | | llvm-svn: 178454
* R600: Emit native instructions for texVincent Lejeune2013-03-312-115/+197
| | | | llvm-svn: 178452
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