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* [PDB] Dump extra info about the publics streamReid Kleckner2017-07-213-5/+5
| | | | | | | | | | This includes the hash table, the address map, and the thunk table and section offset table. The last two are only used for incremental linking, which LLD doesn't support, so they are less interesting. The hash table is particularly important to get right, since this is the one of the streams that debuggers use to translate addresses to symbols. llvm-svn: 308764
* AMDGPU: Fix getMemOpBaseRegImmOfs for flat with offsetsMatt Arsenault2017-07-211-3/+13
| | | | llvm-svn: 308762
* [Hexagon] Add inline-asm constraint 'a' for modifier register classKrzysztof Parzyszek2017-07-211-2/+10
| | | | | | | For example asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory") llvm-svn: 308761
* ThinLTO Minimized Bitcode File Size ReductionHaojie Wang2017-07-212-78/+245
| | | | | | | | | | | | | | Summary: Currently the ThinLTO minimized bitcode file only strip the debug info, but there is still a lot of information in the minimized bit code file that will be not used for thin linker. In this patch, most of the extra information is striped to reduce the minimized bitcode file. Now only ModuleVersion, ModuleInfo, ModuleGlobalValueSummary, ModuleHash, Symtab and Strtab are left. Now the minimized bitcode file size is reduced to 15%-30% of the debug info stripped bitcode file size. Reviewers: danielcdh, tejohnson, pcc Reviewed By: pcc Subscribers: mehdi_amini, aprantl, inglorion, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D35334 llvm-svn: 308760
* [mips] Support -membedded-data and fix a related bugSimon Dardis2017-07-211-2/+15
| | | | | | | | | | | | -membedded-data changes the location of constant data from the .sdata to the .rodata section. Previously it was (incorrectly) always located in the .rodata section. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D35686 llvm-svn: 308758
* [RuntimeUnroll] NFC: Add a profitability function for mutliexit loopAnna Thomas2017-07-211-9/+24
| | | | | | | | | | | Separated out the profitability from the safety analysis for multiexit loop unrolling. Currently, this is an NFC because profitability is true only if the unroll-runtime-multi-exit is set to true (off-by-default). This is to ease adding the profitability heuristic up for review at D35380. llvm-svn: 308753
* [SLPVectorizer] Replace E->Scalars to VL0 at vectorizeTree and move comment, ↵Dinar Temirbulatov2017-07-211-4/+3
| | | | | | NFCI. llvm-svn: 308750
* AMDGPU: Add instruction definitions for some scratch_* instructionsMatt Arsenault2017-07-215-19/+108
| | | | | | Omit atomics for now since they probably aren't useful. llvm-svn: 308747
* [SLPVectorizer] buildTree_rec replace cast<Instruction>(VL[0]) to VL0, NFCI.Dinar Temirbulatov2017-07-211-4/+4
| | | | llvm-svn: 308745
* [mips] Enable IAS by default for Android MIPS64Petar Jovanovic2017-07-211-0/+4
| | | | | | | | | Follow up to r306280 in Clang. Enable IAS by default for Android MIPS64 (uses N64 ABI). Differential Revision: https://reviews.llvm.org/D35482 llvm-svn: 308742
* [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky2017-07-2110-40/+343
| | | | | | | | | | See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591 Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D35424 llvm-svn: 308740
* [SLPVectorizer] Change canReuseExtract function parameter Opcode from ↵Dinar Temirbulatov2017-07-211-19/+15
| | | | | | unsigned to Value *, NFCI. llvm-svn: 308739
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-2129-67/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* [X86][SSE] Add pre-AVX2 support for (i32 bitcast(v32i1)) -> 2xMOVMSKSimon Pilgrim2017-07-211-3/+15
| | | | | | | | | | | | Currently we only support (i32 bitcast(v32i1)) using the AVX2 VPMOVMSKB ymm instruction. This patch adds support for splitting pre-AVX2 targets into 2 x (V)PMOVMSKB xmm instructions and merging the integer results. In future we could probably generalize this to handle more cases. Differential Revision: https://reviews.llvm.org/D35303 llvm-svn: 308723
* Commit access testPhilipp Schaad2017-07-211-1/+1
| | | | llvm-svn: 308712
* Debug Info: Don't strip clang module skeleton CUs.Adrian Prantl2017-07-211-1/+2
| | | | | | | | This corrects a (hopefully :-) accidental side-effect of r304020. rdar://problem/33442618 llvm-svn: 308708
* [DWARF] Generalized verification of .debug_abbrev to be applicable to both ↵Spyridoula Gravani2017-07-211-14/+24
| | | | | | | | .debug_abbrev and .debug_abbrev.dwo sections. Differential Revision: https://reviews.llvm.org/D35698 llvm-svn: 308703
* [AVX-512] Fix a bug that prevented some non-temporal loads from using the ↵Craig Topper2017-07-211-3/+3
| | | | | | | | movntdqa instruction. The bitconverts here had an input type of 128-bits and an output type of 256 bits. The input type should also have been 256 bits. llvm-svn: 308702
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-07-201-10/+16
| | | | | | | Add the cost for the EXT instructions and explicitly add the cost for a few instructions that were implied by the coarse model. llvm-svn: 308697
* Add error handling to the dyld compact export entries in libObject.Kevin Enderby2017-07-201-22/+154
| | | | | | | | | | | | | | | | | | | | | lld needs a matching change for this will be my next commit. Expect it to fail build until that matching commit is picked up by the bots. Like the changes in r296527 for dyld bind entires and the changes in r298883 for lazy bind, weak bind and rebase entries the export entries are the last of the dyld compact info to have error handling added. This follows the model of iterators that can fail that Lang Hanes designed when fixing the problem for bad archives r275316 (or r275361). So that iterating through the exports now terminates if there is an error and returns an llvm::Error with an error message in all cases for malformed input. This change provides the plumbing for the error handling, all the needed testing of error conditions and test cases for all of the unique error messages. llvm-svn: 308690
* Recommit: GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64.Tim Northover2017-07-201-1/+49
| | | | | | | | It revealed a bug in the Localizer pass which has now been fixed. This includes the fix for SUBREG_TO_REG committed separately last time. llvm-svn: 308688
* GlobalISel: stop localizer putting constants before EH_LABELsTim Northover2017-07-201-1/+2
| | | | | | | | If the localizer pass puts one of its constants before the label that tells the unwinder "jump here to handle your exception" then control-flow will skip it, leaving uninitialized registers at runtime. That's bad. llvm-svn: 308687
* Implement parsing and writing of a single xml manifest file.Eric Beckmann2017-07-202-0/+74
| | | | | | | | | | Summary: Implement parsing and writing of a single xml manifest file. Subscribers: mgorny, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D35425 llvm-svn: 308679
* [NVPTX] Add lowering of i128 params.Artem Belevich2017-07-203-11/+32
| | | | | | | | | | | | | | | | | The patch adds support of i128 params lowering. The changes are quite trivial to support i128 as a "special case" of integer type. With this patch, we lower i128 params the same way as aggregates of size 16 bytes: .param .b8 _ [16]. Currently, NVPTX can't deal with the 128 bit integers: * in some cases because of failed assertions like ValVTs.size() == OutVals.size() && "Bad return value decomposition" * in other cases emitting PTX with .i128 or .u128 types (which are not valid [1]) [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types Differential Revision: https://reviews.llvm.org/D34555 Patch by: Denys Zariaiev (denys.zariaiev@gmail.com) llvm-svn: 308675
* AMDGPU: Rename _RTN atomic instructionsMatt Arsenault2017-07-202-26/+26
| | | | | | | | | | | Move the _RTN to the end of the name. It reads better if the other addressing mode components line up with the non-RTN version. It is also more convenient to define saddr variants of FLAT atomics to have the RTN last, and it is good to have a consistent naming scheme. llvm-svn: 308674
* Add an ID field to StackObjectsMatt Arsenault2017-07-206-5/+24
| | | | | | | | | | | | | | | | | | | | | On AMDGPU SGPR spills are really spilled to another register. The spiller creates the spills to new frame index objects, which is used as a placeholder. This will eventually be replaced with a reference to a position in a VGPR to write to and the frame index deleted. It is most likely not a real stack location that can be shared with another stack object. This is a problem when StackSlotColoring decides it should combine a frame index used for a normal VGPR spill with a real stack location and a frame index used for an SGPR. Add an ID field so that StackSlotColoring has a way of knowing the different frame index types are incompatible. llvm-svn: 308673
* Changed EOL back to LF. NFC.Artem Belevich2017-07-202-7832/+7832
| | | | llvm-svn: 308671
* Generate error reports when a fuzz target exits.Matt Morehouse2017-07-2021-20/+59
| | | | | | | | | | | | | | | | | | | | | | Summary: Implements https://github.com/google/sanitizers/issues/835. Flush stdout before exiting in test cases. Since the atexit hook is used for exit reports, pending prints to stdout can be lost if they aren't flushed before calling exit(). Expect tests to have non-zero exit code if exit() is called. Reviewers: vitalybuka, kcc Reviewed By: kcc Subscribers: eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D35602 llvm-svn: 308669
* [PGO] Move the PGOInstrumentation pass to new OptRemark API.Davide Italiano2017-07-201-4/+4
| | | | | | This fixes PR33791. llvm-svn: 308668
* [PEI] Fix refactoring from r308664Francis Visoiu Mistrih2017-07-201-1/+1
| | | | llvm-svn: 308666
* [COFF, ARM64, CodeView] Add support to emit CodeView debug info for ARM64 COFFMandeep Singh Grang2017-07-205-1/+20
| | | | | | | | | | | | Reviewers: compnerd, ruiu, rnk, zturner Reviewed By: rnk Subscribers: majnemer, aemerson, aprantl, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35518 llvm-svn: 308665
* [PEI] Separate saving and restoring CSRs into different functions. NFCFrancis Visoiu Mistrih2017-07-201-66/+51
| | | | | | | | | | | Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores. This is mostly useful for future shrink-wrapping improvements where we want to save / restore a specific part of the CSRs in a specific block. Differential Revision: https://reviews.llvm.org/D35644 llvm-svn: 308664
* [libFuzzer] delete stale codeKostya Serebryany2017-07-201-23/+0
| | | | llvm-svn: 308663
* [SPARC] Clean up the support for disabling fsmuld and fmuls instructions.James Y Knight2017-07-209-279/+25
| | | | | | | | | | | | | | | | | Summary: Also enable no-fsmuld for sparcv7 (which doesn't have the instruction). The previous code which used a post-processing pass to do this was unnecessary; disabling the instruction is entirely sufficient. Reviewers: jacob_hansen, ekedaigle Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35576 llvm-svn: 308661
* Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLaneKrzysztof Parzyszek2017-07-203-6/+5
| | | | | | | This should eliminate most uses of countPopulation and Log2_32 on the lane mask values. llvm-svn: 308658
* [X86] Allow masks with more than 6 bits set on the x << (y & mask) ↵Craig Topper2017-07-201-1/+1
| | | | | | optimization for the 64-bit memory shifts. llvm-svn: 308657
* Use LaneBitmask::getLane in a few more placesKrzysztof Parzyszek2017-07-202-3/+3
| | | | llvm-svn: 308655
* [libFuzzer] make sure CheckExitOnSrcPosOrItem is called after the new input ↵Kostya Serebryany2017-07-202-4/+6
| | | | | | is saved to the corpus llvm-svn: 308653
* [DAG] Commit missed nit cleanup from r308617. NFC.Nirav Dave2017-07-201-1/+1
| | | | llvm-svn: 308645
* LowerTypeTests: Drop function type metadata only if we're going to replace it.Peter Collingbourne2017-07-201-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Previously we were (mis)handling jump table members with a prevailing definition in a full LTO module and a non-prevailing definition in a ThinLTO module by dropping type metadata on those functions entirely, which would cause type tests involving such functions to fail. This patch causes us to drop metadata only if we are about to replace it with metadata from cfi.functions. We also want to replace metadata for available_externally functions, which can arise in the opposite scenario (prevailing ThinLTO definition, non-prevailing full LTO definition). The simplest way to handle that is to remove the definition; there's little value in keeping it around at this point (i.e. after most optimization passes have already run) and later code will try to use the function's linkage to create an alias, which would result in invalid IR if the function is available_externally. Fixes PR33832. Differential Revision: https://reviews.llvm.org/D35604 llvm-svn: 308642
* AMDGPU: Add encoding for carryless add/sub instructionsMatt Arsenault2017-07-205-1/+69
| | | | llvm-svn: 308639
* AMDGPU: Add encodings for global atomicsMatt Arsenault2017-07-201-25/+190
| | | | llvm-svn: 308638
* [DAG] Handle missing transform in fold of value extension case.Nirav Dave2017-07-201-0/+14
| | | | | | | | | | | | | | | Summary: When pushing an extension of a constant bitwise operator on a load into the load, change other uses of the load value if they exist to prevent the old load from persisting. Reviewers: spatel, RKSimon, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35030 llvm-svn: 308618
* [DAG] Optimize away degenerate INSERT_VECTOR_ELT nodes.Nirav Dave2017-07-201-0/+6
| | | | | | | | | | | | | | | | | Summary: Add missing vector write of vector read reduction, i.e.: (insert_vector_elt x (extract_vector_elt x idx) idx) to x Reviewers: spatel, RKSimon, efriedma Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35563 llvm-svn: 308617
* Reland r308585Stefan Maksimovic2017-07-208-42/+71
| | | | | | | | Builder clang-x86_64-linux-abi-test apparently failed due to a spurious error unrelated to the changes r308585 introduced. llvm-svn: 308612
* [ARM] Simplify ExpandPseudoInst. NFC.Javed Absar2017-07-201-10/+2
| | | | | | | | | Remove headers not required and convert to range-loop Reviewed by: @mcrosier Differential Revision: https://reviews.llvm.org/D35626 llvm-svn: 308607
* [mips] Support `long_call/far/near` attributes passed by front-endSimon Atanasyan2017-07-201-9/+24
| | | | | | | | | This patch adds handling of the `long_call`, `far`, and `near` attributes passed by front-end. The patch depends on D35479. Differential revision: https://reviews.llvm.org/D35480. llvm-svn: 308606
* Revert "GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64."Diana Picus2017-07-201-48/+1
| | | | | | | This reverts commit 36c6a2ea9669bc3bb695928529a85d12d1d3e3f9 because it broke the test-suite on the GlobalISel bot. llvm-svn: 308603
* [DAGCombiner] Match ISD::SRL non-uniform constant vectors patterns using ↵Simon Pilgrim2017-07-201-13/+26
| | | | | | | | predicates. Use predicate matchers introduced in D35492 to match more ISD::SRL constant folds llvm-svn: 308602
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-07-201-1/+1
| | | | llvm-svn: 308601
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