summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [C++11] Mark more classes in the X86 target as 'final'.Craig Topper2014-03-316-8/+8
| | | | llvm-svn: 205166
* Mark a couple of the X86 target classes as final. Allows the compiler to ↵Craig Topper2014-03-312-2/+2
| | | | | | de-virtualize some internal calls. llvm-svn: 205165
* ARM64CollectLOH.cpp: Tweak \param. [-Wdocumentation]NAKAMURA Takumi2014-03-311-1/+1
| | | | llvm-svn: 205162
* [ARM64] Fix materialization of an fp128 zero immediate. There currentlyChandler Carruth2014-03-311-2/+3
| | | | | | | | | is not a pattern to lower this with clever instructions that zero the register, so restrict the zero immediate legality special case to f64 and f32 (the only two sizes which fmov seems to directly support). Fixes backend errors when building code such as libxml. llvm-svn: 205161
* [X86] Adjust cost of FP_TO_UINT v8f32->v8i32Adam Nemet2014-03-301-0/+6
| | | | | | | | | | | | | | | There is no direct AVX instruction to convert to unsigned. I have some ideas how we may be able to do this with three vector instructions but the current backend just bails on this to get it scalarized. See the comment why we need to adjust the cost returned by BasicTTI. The test is a bit roundabout (and checks assembly rather than bit code) because I'd like it to work even if at some point we could vectorize this conversion. Fixes <rdar://problem/16371920> llvm-svn: 205159
* PR18929:Stepan Dyatkovskiy2014-03-301-16/+22
| | | | | | | | According to ARM assembler language hash symbol is optional before immediates. For example, see here for more details: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473j/dom1359731154529.html llvm-svn: 205157
* Make use of previously generated stores in ↵Hal Finkel2014-03-301-4/+33
| | | | | | | | | | | | | | | | | SelectionDAGLegalize::ExpandExtractFromVectorThroughStack When expanding EXTRACT_VECTOR_ELT and EXTRACT_SUBVECTOR using SelectionDAGLegalize::ExpandExtractFromVectorThroughStack, we store the entire vector and then load the piece we want. This is fine in isolation, but generating a new store (and corresponding stack slot) for each extraction ends up producing code of poor quality. When we scalarize a vector operation (using SelectionDAG::UnrollVectorOp for example) we generate one EXTRACT_VECTOR_ELT for each element in the vector. This used to generate one stored copy of the vector for each element in the vector. Now we search the uses of the vector for a suitable store before generating a new one, which results in much more efficient scalarization code. llvm-svn: 205153
* [PowerPC] Handle VSX v2i64 SIGN_EXTEND_INREGHal Finkel2014-03-303-0/+45
| | | | | | | | | | | | | | | | sitofp from v2i32 to v2f64 ends up generating a SIGN_EXTEND_INREG v2i64 node (and similarly for v2i16 and v2i8). Even though there are no sign-extension (or algebraic shifts) for v2i64 types, we can handle v2i32 sign extensions by converting two and from v2i64. The small trick necessary here is to shift the i32 elements into the right lanes before the i32 -> f64 step. This is because of the big Endian nature of the system, we need the i32 portion in the high word of the i64 elements. For v2i16 and v2i8 we can do the same, but we first use the default Altivec shift-based expansion from v2i16 or v2i8 to v2i32 (by casting to v4i32) and then apply the above procedure. llvm-svn: 205146
* [Allocator] Lift the slab size and size threshold into templateChandler Carruth2014-03-302-135/+20
| | | | | | | | | | parameters rather than runtime parameters. There is only one user of these parameters and they are compile time for that user. Making these compile time seems to better reflect their intended usage as well. llvm-svn: 205143
* Don't mark the declarations of the TSan annotation functions as weak.Chandler Carruth2014-03-301-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | That causes references to them to be weak references which can collapse to null if no definition is provided. We call these functions unconditionally, so a definition *must* be provided. Make the definitions provided in the .cpp file weak by re-declaring them as weak just prior to defining them. This should keep compilers which cannot attach the weak attribute to the definition happy while actually resolving the symbols correctly during the link. You might ask yourself upon reading this commit log: how did *any* of this work before? Well, fun story. It turns out we have some code in Support (BumpPtrAllocator) which both uses virtual dispatch and has out-of-line vtables used by that virtual dispatch. If you move the virtual dispatch into its header in *just* the right way, the optimizer gets to devirtualize, and remove all references to the vtable. Then the sad part: the references to this one vtable were the only strong symbol uses in the support library for llvm-tblgen AFAICT. At least, after doing something just like this, these symbols stopped getting their weak definition and random calls to them would segfault instead. Yay software. llvm-svn: 205137
* [ARM64] Fix a heap-use-after-free spotted by ASan.Chandler Carruth2014-03-301-1/+1
| | | | | | | | StringRef::lower() returns a std::string. Better yet, we can now stop thinking about what it returns and write 'auto'. It does the right thing. =] llvm-svn: 205135
* ARM64: uncopy/paste helper functionTim Northover2014-03-301-5/+4
| | | | | | | | | It was doing functional but highly suspect operations on bools due to the more limited shifting operands supported by memory instructions. Should fix some MSVC warnings. llvm-svn: 205134
* ARM64: remove unused variablesTim Northover2014-03-301-4/+0
| | | | llvm-svn: 205133
* ARM64: remove -m32/-m64 mapping with ARM.Tim Northover2014-03-301-2/+2
| | | | | | | This is causing the ARM build-bots to fail since they only include the ARM backend and can't create an ARM64 target. llvm-svn: 205132
* ARM64: override all the things.Tim Northover2014-03-307-149/+148
| | | | | | | | Actually, mostly only those in the top-level directory that already had a "virtual" attached. But it's the thought that counts and it's been a long day. llvm-svn: 205131
* Support: correct Windows normalisationSaleem Abdulrasool2014-03-301-2/+12
| | | | | | | | | | | | | If the environment is unknown and no object file is provided, then assume an "MSVC" environment, otherwise, set the environment to the object file format. In the case that we have a known environment but a non-native file format for Windows (COFF) which is used for MCJIT, then append the custom file format to the triple as an additional component. This fixes the MCJIT tests on Windows. llvm-svn: 205130
* X86Subtarget.h: isTargetWindows() should tell whether he is targeting msvc.NAKAMURA Takumi2014-03-301-2/+1
| | | | | | | FYI, !isWindowsGNUEnvironment() is insufficient. It missed cygwin. FIXME: The name "isTargetWindows" should be fixed. llvm-svn: 205124
* [MC] Remove an unused (and broken) variant of the setupForSymbolicDisassemblyLang Hames2014-03-301-8/+0
| | | | | | method in MCDisassembler. llvm-svn: 205123
* Add a missing break.Rafael Espindola2014-03-301-0/+1
| | | | | | | | | | Patch by Tobias Güntner. I tried to write a test, but the only difference is the Changed value that gets returned. It can be tested with "opt -debug-pass=Executions -functionattrs, but that doesn't seem worth it. llvm-svn: 205121
* Support: normalize the default triple on UnixSaleem Abdulrasool2014-03-301-1/+1
| | | | | | | | | | This will fix cross-compiling buildbots (e.g. cygwin). This is in the same vein as SVN r205070. Apply this to fix the cross-compiling scenario, even though the preferred solution is to update the build system to normalize the embedded triple rather than perform this at runtime every time. This is meant to tide us over until that approach is fleshed out and applied. llvm-svn: 205120
* Fix a few -Wdocumentation warningsDmitri Gribenko2014-03-294-13/+13
| | | | llvm-svn: 205116
* Detemplatize LOHDirective.Benjamin Kramer2014-03-293-25/+25
| | | | | | | | | | | The ARM64 backend uses it only as a container to keep an MCLOHType and Arguments around so give it its own little copy. The other functionality isn't used and we had a crazy method specialization hack in place to keep it working. Unfortunately that was incompatible with MSVC. Also range-ify a couple of loops while at it. llvm-svn: 205114
* ARM64: Remove unused helper function, make others static.Benjamin Kramer2014-03-293-45/+6
| | | | llvm-svn: 205112
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-292-22/+22
| | | | | | No functionality change. llvm-svn: 205110
* Avoid storing Twines.Benjamin Kramer2014-03-291-22/+19
| | | | | | While there nested ifs into a helper function. No functionality change. llvm-svn: 205108
* [PowerPC] Handle v2i64 comparisonsHal Finkel2014-03-291-0/+23
| | | | | | | | v2i64 is a legal type under VSX, however we don't have native vector comparisons. We can handle eq/ne by casting it to an Altivec type, but everything else must be expanded. llvm-svn: 205106
* ARM64: format register strings without creating a local Twine.Tim Northover2014-03-291-5/+5
| | | | | | It was causing horrible failures on some build-bots. llvm-svn: 205105
* [PowerPC] VSX instruction latency correctionsHal Finkel2014-03-292-15/+15
| | | | | | | | The vector divide and sqrt instructions have high latencies, and the scalar comparisons are like all of the others. On the P7, permutations take an extra cycle over purely-simple vector ops. llvm-svn: 205096
* Recommitted fix for PR18931, with extended tests set.Stepan Dyatkovskiy2014-03-292-2/+20
| | | | | | | | | | | | | Issue subject: Crash using integrated assembler with immediate arithmetic Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 205094
* ARM64: use 64-bit constant even on 32-bit machinesTim Northover2014-03-291-1/+1
| | | | | | Another existing bot failure so no tests. llvm-svn: 205093
* ARM64: change format specifier to work on 32-bit targetsTim Northover2014-03-291-1/+1
| | | | | | Existing tests were failing. llvm-svn: 205092
* [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it isChandler Carruth2014-03-293-3/+3
| | | | | | | | | | | no assert at all. ;] Some of these should probably be switched to llvm_unreachable, but I didn't want to perturb the behavior in this patch. Found by -Wstring-conversion, which I'll try to turn on in CMake builds at least as it is finding useful things. llvm-svn: 205091
* ARM64: initial backend importTim Northover2014-03-2995-14/+58771
| | | | | | | | | | | | This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
* CodeGen: add sensible defaults for the ISD::FROUND operationTim Northover2014-03-291-0/+9
| | | | | | Some exotic types didn't know how to handle FROUND, which ARM64 uses. llvm-svn: 205088
* MC-exceptions: add support for compact-unwind without .eh_frameTim Northover2014-03-292-3/+22
| | | | | | | | | | | | ARM64 has compact-unwind information, but doesn't necessarily want to emit .eh_frame directives as well. This teaches MC about such a situation so that it will skip .eh_frame info when compact unwind has been successfully produced. For functions incompatible with compact unwind, the normal information is still written. llvm-svn: 205087
* CodeGenPrep: wrangle IR to exploit AArch64 tbz/tbnz inst.Tim Northover2014-03-292-0/+81
| | | | | | | | | | | | | | | | Given IR like: %bit = and %val, #imm-with-1-bit-set %tst = icmp %bit, 0 br i1 %tst, label %true, label %false some targets can emit just a single instruction (tbz/tbnz in the AArch64 case). However, with ISel acting at the basic-block level, all three instructions need to be together for this to be possible. This adds another transformation to CodeGenPrep to expose these opportunities, if targets opt in via the hook. llvm-svn: 205086
* MC: add a RefKind field to MCValueTim Northover2014-03-291-0/+5
| | | | | | | | This is principally to allow neater mapping of fixups to relocations in ARM64 ELF. Without this, there isn't enough information available to GetRelocType, leading to many more fixup_arm64_... enumerators. llvm-svn: 205085
* MachO: Add linker-optimisation hint framework to MC.Tim Northover2014-03-296-2/+86
| | | | | | | | Another part of the ARM64 backend (so tests will be following soon). This is currently used by the linker to relax adrp/ldr pairs into nops where possible, though could well be more broadly applicable. llvm-svn: 205084
* MachO: actually set linker-private prefix at MC level.Tim Northover2014-03-291-0/+1
| | | | | | This was accidentally omitted from r205081. llvm-svn: 205083
* MachO: allow each section to have a linker-private symbolTim Northover2014-03-293-4/+41
| | | | | | | | | The upcoming ARM64 backend doesn't have section-relative relocations, so we give each section its own symbol to provide this functionality. Of course, it doesn't need to appear in the final executable, so linker-private is the best kind for this purpose. llvm-svn: 205081
* Intrinsics: add LLVMHalfElementsVectorType constraintTim Northover2014-03-292-1/+17
| | | | | | | | | | This is like the LLVMMatchType, except the verifier checks that the second argument is a vector with the same base type and half the number of elements. This will be used by the ARM64 backend. llvm-svn: 205079
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-2923-637/+308
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* [PowerPC] Add subregister classes for f64 VSX valuesHal Finkel2014-03-298-59/+192
| | | | | | | | | | | | | We had stored both f64 values and v2f64, etc. values in the VSX registers. This worked, but was suboptimal because we would always spill 16-byte values even through we almost always had scalar 8-byte values. This resulted in an increase in stack-size use, extra memory bandwidth, etc. To fix this, I've added 64-bit subregisters of the Altivec registers, and combined those with the existing scalar floating-point registers to form a class of VSX scalar floating-point registers. The ABI code has also been enhanced to use this register class and some other necessary improvements have been made. llvm-svn: 205075
* Windows: canonicalise the default windows tripleSaleem Abdulrasool2014-03-291-1/+1
| | | | | | | Canonicalise the default triple that is used on Windows. This should hopefully fix the MSVC buildbots. llvm-svn: 205070
* [x86] Fix printing of register operands with q modifier.Akira Hatanaka2014-03-281-3/+5
| | | | | | | | | Emit 32-bit register names instead of 64-bit register names if the target does not have 64-bit general purpose registers. <rdar://problem/14653996> llvm-svn: 205067
* Debug Compression: Avoid compression debug_frame for nowDavid Blaikie2014-03-281-1/+1
| | | | | | | | Turns out debug_frame does use multiple fragments, so it doesn't compress correctly with the current approach. Disable compressing it for now while I figure out what's the best solution for it. llvm-svn: 205059
* X86: Disable IsLegalToCallImmediateAddr for Win32David Majnemer2014-03-281-1/+4
| | | | | | | | | | WinCOFF cannot form PC relative relocations to support absolute MCValues. We should reenable this once WinCOFF supports emission of IMAGE_REL_I386_REL32 relocations. This fixes PR19272. llvm-svn: 205058
* [PowerPC] Fix VSX permutation iselHal Finkel2014-03-281-1/+1
| | | | | | | Not only did I invert the indices when I wrote the code, but I also did the same thing when I wrote the regression test. Oops. llvm-svn: 205046
* [PowerPC] v2[fi]64 need to be explicitly passed in VSX registersHal Finkel2014-03-282-7/+36
| | | | | | | | v2[fi]64 values need to be explicitly passed in VSX registers. This is because the code in TRI that finds the minimal register class given a register and a value type will assert if given an Altivec register and a non-Altivec type. llvm-svn: 205041
* Map ELf flags back to more specific section kinds.Rafael Espindola2014-03-281-2/+28
| | | | | | With that, convert another llc -filetype=obj test. llvm-svn: 205031
OpenPOWER on IntegriCloud