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* [objc-arc] Added descriptions for EnableARCAnnotations, ↵Michael Gottesman2013-04-172-3/+7
| | | | | | EnableCheckForCFGHazards, EnableARCOptimizations. llvm-svn: 179718
* [objc-arc] Added an option to arc-annotations for turning off CheckForCFGHazard.Michael Gottesman2013-04-171-0/+6
| | | | llvm-svn: 179717
* This patch teaches x86 fast-isel to generate the native div/idiv instructionsEli Bendersky2013-04-171-0/+125
| | | | | | | | | for the sdiv/srem/udiv/urem bitcode instructions. This is done for the i8, i16, and i32 types, as well as i64 for the x86_64 target. Patch by Jim Stichnoth llvm-svn: 179715
* X86 cost model: Exit before calling getSimpleVT on non-simple VTsArnold Schwaighofer2013-04-171-0/+4
| | | | | | | | getSimpleVT can only handle simple value types. radar://13676022 llvm-svn: 179714
* A limit of 500 was still a bit too high for some tests.Bill Wendling2013-04-171-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR15000 has a testcase where the time to compile was bordering on 30s. When I dropped the limit value to 100, it became a much more managable 6s. The compile time seems to increase in a roughly linear fashion based on increasing the limit value. (See the runtimes below.) So, let's lower the limit to 100 so that they can get a more reasonable compile time. Limit Value Time ----------- ---- 10 0.9744s 20 1.8035s 30 2.3618s 40 2.9814s 50 3.6988s 60 4.5486s 70 4.9314s 80 5.8012s 90 6.4246s 100 7.0852s 110 7.6634s 120 8.3553s 130 9.0552s 140 9.6820s 150 9.8804s 160 10.8901s 170 10.9855s 180 12.0114s 190 12.6816s 200 13.2754s 210 13.9942s 220 13.8097s 230 14.3272s 240 15.7753s 250 15.6673s 260 16.0541s 270 16.7625s 280 17.3823s 290 18.8213s 300 18.6120s 310 20.0333s 320 19.5165s 330 20.2505s 340 20.7068s 350 21.1833s 360 22.9216s 370 22.2152s 380 23.9390s 390 23.4609s 400 24.0426s 410 24.6410s 420 26.5208s 430 27.7155s 440 26.4142s 450 28.5646s 460 27.3494s 470 29.7255s 480 29.4646s 490 30.5001s llvm-svn: 179713
* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-173-4/+29
| | | | | | | | | | | | | | | The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction: 1. nop (imm == 0) 2. yield (imm == 1) 3. wfe (imm == 2) 4. wfi (imm == 3) 5. sev (imm == 4) Therefore, restrict the permitted values for the "hint" instruction to 0 through 4. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179707
* Appease a gcc warning about an overflow in a constant conversion.Bill Wendling2013-04-171-1/+2
| | | | llvm-svn: 179703
* Don't store AttributeSet::FunctionIndex as an int.Benjamin Kramer2013-04-171-1/+1
| | | | | | | | GCC complains: Core.cpp:1449:27: warning: overflow in implicit constant conversion [-Woverflow] I'm not sure if that's really a problem here, but using the enum type is better style anyways. llvm-svn: 179696
* PowerPC: Mark some more patterns as isCodeGenOnly.Ulrich Weigand2013-04-172-0/+6
| | | | | | | | | | A couple of recently introduced conditional branch patterns also need to be marked as isCodeGenOnly since they cannot be handled by the asm parser. No change in generated code. llvm-svn: 179690
* R600: Make Export Instruction not duplicableVincent Lejeune2013-04-171-1/+3
| | | | llvm-svn: 179686
* R600: Export is emitted as a CF_NATIVE instVincent Lejeune2013-04-172-14/+9
| | | | llvm-svn: 179685
* R600: Emit used GPRs countVincent Lejeune2013-04-172-8/+41
| | | | llvm-svn: 179684
* Use StringSwitch instead of long chain of if-else. No functionality change.Alexey Samsonov2013-04-171-37/+28
| | | | llvm-svn: 179682
* Create a stub for DWARF parser unittestsAlexey Samsonov2013-04-174-85/+3
| | | | | | | Moves one DWARF-specific header to include/llvm/DebugInfo from lib/. Add a short unittest for r179095. llvm-svn: 179678
* Fix -Werror build.Evgeniy Stepanov2013-04-171-0/+2
| | | | | | Broken in r179657. llvm-svn: 179669
* PR15149/r174304 improvement - print hex for unknown dwarf language codes & ↵David Blaikie2013-04-171-2/+7
| | | | | | | | add a test case CR feedback from Rafael Espindola and Paul Robinson. llvm-svn: 179664
* Do not optimise fprintf() calls if its return value is used.Peter Collingbourne2013-04-171-9/+12
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D620 llvm-svn: 179661
* Mips assembler: Enable handling of nested expressionsJack Carter2013-04-172-133/+237
| | | | | | | | | | This patch allows the Mips assembler to parse and emit nested expressions as instruction operands. It also extends the expansion of memory instructions when an offset is given as an expression. Contributer: Vladimir Medic llvm-svn: 179657
* [ms-inline asm] Add support for parsing complex immediate expressions. TestChad Rosier2013-04-171-32/+51
| | | | | | | cases to be submitted on clang side shortly. rdar://13663768 and PR15760 llvm-svn: 179655
* C API: Add LLVMTargetMachineEmitToMemoryBuffer()Tom Stellard2013-04-161-12/+33
| | | | llvm-svn: 179648
* C API: Add LLVMGetBufferSize()Tom Stellard2013-04-161-0/+4
| | | | llvm-svn: 179647
* C API: Add LLVMGetBufferStart()Tom Stellard2013-04-161-0/+3
| | | | llvm-svn: 179646
* C API: Add LLVMAddTargetDependentFunctionAttr()Tom Stellard2013-04-161-0/+11
| | | | llvm-svn: 179645
* Print out the target-independent attributes in a comment before the function ↵Bill Wendling2013-04-161-4/+24
| | | | | | definition. llvm-svn: 179622
* Remove unused variable from previous refactor.Chad Rosier2013-04-161-3/+0
| | | | llvm-svn: 179611
* [ms-inline asm] Refactor. No functional change intended.Chad Rosier2013-04-161-405/+419
| | | | llvm-svn: 179610
* [ms-inline asm] Remove some dead code.Chad Rosier2013-04-161-8/+0
| | | | llvm-svn: 179607
* Cleanup naming: DataLayout s/TD/DL/Eli Bendersky2013-04-161-3/+3
| | | | llvm-svn: 179601
* Fix build failure introduced in 179591 when assertions are disabled.Logan Chien2013-04-161-0/+4
| | | | llvm-svn: 179593
* Implement ARM unwind opcode assembler.Logan Chien2013-04-165-45/+427
| | | | llvm-svn: 179591
* Add four new functions and one new enum to the C API:Hans Wennborg2013-04-161-0/+47
| | | | | | | | | | | | LLVMGetThreadLocalMode - exposes GlobalVariable::getThreadLocalMode LLVMSetThreadLocalMode - exposes GlobalVariable::setThreadLocalMode LLVMIsExternallyInitialized - exposes GlobalVariable::isExternallyInitialized LLVMSetExternallyInitialized - exposes GlobalVariable::setExternallyInitialized LLVMThreadLocalMode - maps to GlobalVariable::ThreadLocalMode Patch by Moritz Maxeiner! llvm-svn: 179588
* simplifycfg: Fix integer overflow converting switch into icmp.Hans Wennborg2013-04-161-1/+6
| | | | | | | | | | | If a switch instruction has a case for every possible value of its type, with the same successor, SimplifyCFG would replace it with an icmp ult, but the computation of the bound overflows in that case, which inverts the test. Patch by Jed Davis! llvm-svn: 179587
* Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen2013-04-162-0/+42
| | | | llvm-svn: 179582
* ARM: Add VACLT and VACLE assembly aliases.Jim Grosbach2013-04-152-0/+19
| | | | | | | | | These are aliases for VACGT and VACGE, respectively, with the source operands reversed. rdar://13638090 llvm-svn: 179575
* We are not able to bitcast a pointer to an integral value.Bill Wendling2013-04-151-5/+5
| | | | | | | | Two return types are not equivalent if one is a pointer and the other is an integral. This is because we cannot bitcast a pointer to an integral value. PR15185 llvm-svn: 179569
* Mips assembler: Explicit floating point condition register recognition.Jack Carter2013-04-151-0/+3
| | | | | | | | | | This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic llvm-svn: 179567
* SLPVectorizer: Make it a function pass and add code for hoisting the ↵Nadav Rotem2013-04-154-163/+256
| | | | | | vector-gather sequence out of loops. llvm-svn: 179562
* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-152-3/+38
| | | | | | | | Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
* R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard2013-04-151-1/+9
| | | | llvm-svn: 179545
* R600: Emit ELF formatted code rather than raw ISA.Tom Stellard2013-04-155-12/+63
| | | | llvm-svn: 179544
* Fix a typo in comment.Jim Grosbach2013-04-151-1/+1
| | | | llvm-svn: 179542
* Make the host endianness check an integer constant expression.Rafael Espindola2013-04-155-10/+10
| | | | | | | | | | | | | | | I will remove the isBigEndianHost function once I update clang. The ifdef logic is designed to * not use configure/cmake to avoid breaking -arch i686 -arch ppc. * default to little endian * be as small as possible It looks like sys/endian.h is the preferred header on most modern BSD systems, but it is better to change this in a followup patch as machine/endian.h is available on FreeBSD, OpenBSD, NetBSD and OS X. llvm-svn: 179527
* Replace uses of the deprecated std::auto_ptr with OwningPtr.Andy Gibbs2013-04-151-23/+22
| | | | | | This is a rework of the broken parts in r179373 which were subsequently reverted in r179374 due to incompatibility with C++98 compilers. This version should be ok under C++98. llvm-svn: 179520
* Add an option -vectorize-slp-aggressive for running the BB vectorizer. Make ↵Nadav Rotem2013-04-151-1/+12
| | | | | | -fslp-vectorize run the slp-vectorizer. llvm-svn: 179508
* Rename the slp-vectorizer clang/llvm flags. No functionality change.Nadav Rotem2013-04-151-3/+3
| | | | llvm-svn: 179505
* SLPVectorizer: Add support for vectorizing trees that start at compare ↵Nadav Rotem2013-04-151-21/+40
| | | | | | instructions. llvm-svn: 179504
* Mark all PPC comparison instructions as not having side effectsHal Finkel2013-04-152-20/+28
| | | | | | | | | | Now that the CR spilling issues have been resolved, we can remove the unmodeled-side-effect attributes from the comparison instructions (and also mark them as isCompare). By allowing these, by default, to have unmodeled side effects, we were hiding problems with CR spilling; but everything seems much happier now. llvm-svn: 179502
* Fix PPC64 CR spill location for callee-saved registersHal Finkel2013-04-152-35/+50
| | | | | | | | | | | | | | | | This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). llvm-svn: 179500
* Use object file specific section type for initial text sectionNico Rieck2013-04-142-12/+3
| | | | llvm-svn: 179494
* Reorders two transforms that collide with each otherDavid Majnemer2013-04-141-8/+8
| | | | | | | | | | | | | | | | | | | | | | One performs: (X == 13 | X == 14) -> X-13 <u 2 The other: (A == C1 || A == C2) -> (A & ~(C1 ^ C2)) == C1 The problem is that there are certain values of C1 and C2 that trigger both transforms but the first one blocks out the second, this generates suboptimal code. Reordering the transforms should be better in every case and allows us to do interesting stuff like turn: %shr = lshr i32 %X, 4 %and = and i32 %shr, 15 %add = add i32 %and, -14 %tobool = icmp ne i32 %add, 0 into: %and = and i32 %X, 240 %tobool = icmp ne i32 %and, 224 llvm-svn: 179493
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