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* Fix code causing fallthrough warnings in the PPC back end.Nemanja Ivanovic2017-12-154-1/+7
| | | | llvm-svn: 320806
* [RISCV] Change shift amount operand of RVC shift instructions to ↵Alex Bradbury2017-12-152-9/+33
| | | | | | | | | | | | | | uimmlog2xlennonzero c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C. This patch adds uimmlog2xlennonzero to reflect this constraint as well as tests. Differential Revision: https://reviews.llvm.org/D41216 Patch by Shiva Chen. llvm-svn: 320799
* Fix the build bot break introduced by r320791.Nemanja Ivanovic2017-12-151-1/+6
| | | | llvm-svn: 320798
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-151-3/+1
| | | | | | | | | | | | | | | | | | This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
* [PM] port Rewrite Statepoints For GC to the new pass manager.Fedor Sergeev2017-12-154-62/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The port is nearly straightforward. The only complication is related to the analyses handling, since one of the analyses used in this module pass is domtree, which is a function analysis. That requires asking for the results of each function and disallows a single interface for run-on-module pass action. Decided to copy-paste the main body of this pass. Most of its code is requesting analyses anyway, so not that much of a copy-paste. The rest of the code movement is to transform all the implementation helper functions like stripNonValidData into non-member statics. Extended all the related LLVM tests with new-pass-manager use. No failures. Reviewers: sanjoy, anna, reames Reviewed By: anna Subscribers: skatkov, llvm-commits Differential Revision: https://reviews.llvm.org/D41162 llvm-svn: 320796
* [LLVMgold] Don't set undefined symbol as prevailingEugene Leviant2017-12-151-1/+4
| | | | | | Differential revision: https://reviews.llvm.org/D41113 llvm-svn: 320794
* [PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic2017-12-159-48/+1041
| | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary infrastructure to convert instructions that take two register operands to those that take a register and immediate if the necessary operand is produced by a load-immediate. Furthermore, it uses this infrastructure to perform such conversions twice - first at MachineSSA and then pre-emit. There are a number of reasons we may end up with opportunities for this transformation, including but not limited to: - X-Form instructions chosen since the exact offset isn't available at ISEL time - Atomic instructions with constant operands (we will add patterns for this in the future) - Tail duplication may duplicate code where one block contains this redundancy - When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant comparands specially Furthermore, this patch moves the initialization of PPCMIPeepholePass so that it can be used for MIR tests. llvm-svn: 320791
* [X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering.Craig Topper2017-12-151-9/+9
| | | | | | | | A couple places didn't use the same SDValue variables to connect everything all the way through. I don't have a test case for a bug in insert into the lower bits of a non-zero, non-undef vector. Not sure the best way to create that. We don't create the case when lowering concat_vectors which is the main way to get insert_subvectors. llvm-svn: 320790
* [SCEV] Fix the movement of insertion point in expander. PR35406.Serguei Katkov2017-12-151-1/+19
| | | | | | | | | | | | We cannot move the insertion point to header if SCEV contains div/rem operations due to they may go over check for zero denominator. Reviewers: sanjoy, mkazantsev, sebpop Reviewed By: sebpop Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41229 llvm-svn: 320789
* Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-153-11/+19
| | | | | | The regression on ppc64 was not due to this commit. llvm-svn: 320788
* Disabling r312514 as it causes miscompiles that show up on bootstrapNemanja Ivanovic2017-12-151-1/+1
| | | | | | | | | | | | The compare elimination peephole introduced in https://reviews.llvm.org/rL312514 causes a miscompile in AMDGPUInstrInfo.cpp which in turn causes some AMDGPU test case failures in stage2 bootstrap testing. This miscompile didn't cause any test case failures until https://reviews.llvm.org/rL320614, so it appeared as if that patch caused these failures. Disabling this transformation for now to bring the build bots back to green and the author of the patch will investigate the miscompile. llvm-svn: 320786
* [X86] Add a TODO about v8i1 CONCAT_VECTORS.Craig Topper2017-12-151-0/+3
| | | | llvm-svn: 320784
* [SelectionDAG] Make getNode calls that take an ArrayRef of SDValue for ↵Craig Topper2017-12-151-4/+7
| | | | | | | | | | operands call NewSDValueDbgMsg. This makes it work better with some build_vector and concat_vectors creations. Adjust the NewSDValueDbgMsg in getConstant to avoid duplicating the print when it calls getSplatBuildVector since getSplatBuildVector didn't trigger a print before. llvm-svn: 320783
* [X86] Further rearrange the setOperationAction calls to separate the ones ↵Craig Topper2017-12-151-66/+83
| | | | | | | | | | | | that require 512-bit registers OR VLX into separate sections. NFCI We have several instructions that were introduced in AVX512F that are only available in 512-bit form on KNL. We still make use of them for 128/256 by artificially widening and extracting during isel. This commit separates these operations from the true 512-bit operations. This way we can qualify the normal 512-bit operations with needing 512-bit register support. And these special operations will get qualified with needing 512-bit registers OR VLX. The 512-bit register qualification will be introduced in a future patch this just gets everything grouped to minimize deltas on that patch. llvm-svn: 320782
* [X86] Group setOperationActions related to vXi1 masks together. NFCICraig Topper2017-12-151-74/+71
| | | | | | | | Previously they were sort of interleaved in with XMM/YMM/ZMM action related code. Trying to separate things so its easier to split 512-bit vectors later. llvm-svn: 320781
* [X86] Make ISD::INSERT_SUBVECTOR v8i1 legal with AVX512F because we should ↵Craig Topper2017-12-151-1/+1
| | | | | | | | be custom lowering inserting v1i1 into v8i1 under this. I don't have a test case at the moment. Just noticed while auditing things. llvm-svn: 320780
* [X86] Move some of the hasVLX qualified code out of the main hasAVX512 block ↵Craig Topper2017-12-151-34/+51
| | | | | | | | | | in the X86ISelLowering constructor. NFCI Move it into the separate hasVLX block later in the constructor. I'm trying to separate 128/256 and 512-bit related code so we can eventually qualify the hasAVX512 block with support for 512-bit vectors required by the prefer-vector-width feature support being talked about in D41096. llvm-svn: 320779
* FastISel: support no-PLT PIC calls on ELF x86_64Saleem Abdulrasool2017-12-151-4/+2
| | | | | | | | | | Add support for properly handling PIC code with no-PLT. This equates to `-fpic -fno-plt -O0` with the clang frontend. External functions are marked with nonlazybind, which must then be indirected through the GOT. This allows code to be built without optimizations in PIC mode without going through the PLT. Addresses PR35653! llvm-svn: 320776
* [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtorsSam Clegg2017-12-156-6/+285
| | | | | | | | | | | | | | | Summary: - lowers @llvm.global_dtors by adding @llvm.global_ctors functions which register the destructors with `__cxa_atexit`. - impements @llvm.global_ctors with wasm start functions and linker metadata See [here](https://github.com/WebAssembly/tool-conventions/issues/25) for more background. Subscribers: jfb, dschuff, mgorny, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41211 llvm-svn: 320774
* Remove a non-modular header (& inline it into its one use)David Blaikie2017-12-142-68/+55
| | | | llvm-svn: 320768
* [AArch64] Test patchEvandro Menezes2017-12-141-0/+1
| | | | | | Fix formatting by adding a missing blank line to test new network setup. llvm-svn: 320760
* EmitFuncArgumentDbgValue: Prefer stack slots over registers for stack argumentsAdrian Prantl2017-12-141-7/+7
| | | | | | | | | | | | | | | | | | While investigating LLVM PR22316 (http://llvm.org/bugs/show_bug.cgi?id=22316) I started wondering if it were not always preferable to emit the initial DBG_VALUEs for stack arguments as FI locations instead of describing the first register they get copied into. The advantage of doing this is that the arguments will be available as soon as the stack is setup. As illustrated by the testcase in the PR, the first copy of the FI into a register may be sunk by MachineSink.cpp into a later basic block. By describing the argument on the stack, we nicely circumvent this problem. <rdar://problem/19583723> Differential Revision: https://reviews.llvm.org/D41135 llvm-svn: 320758
* [X86] Remove an unnecessary SmallVector that was collecting chains for two ↵Craig Topper2017-12-141-5/+3
| | | | | | | | SDNode's we're still holding SDValues for. NFCI We can just get the chains from those SDValues to create the TokenFactor. llvm-svn: 320757
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-1416-3/+19
| | | | llvm-svn: 320756
* Fix many -Wsign-compare and -Wtautological-constant-compare warnings.Zachary Turner2017-12-149-10/+10
| | | | | | | | | | | | Most of the -Wsign-compare warnings are due to the fact that enums are signed by default in the MS ABI, while the tautological comparison warnings trigger on x86 builds where sizeof(size_t) is 4 bytes, so N > numeric_limits<unsigned>::max() is always false. Differential Revision: https://reviews.llvm.org/D41256 llvm-svn: 320750
* [SimplifyCFG] don't sink common insts too soon (PR34603)Sanjay Patel2017-12-146-15/+36
| | | | | | | | | | | | This should solve: https://bugs.llvm.org/show_bug.cgi?id=34603 ...by preventing SimplifyCFG from altering redundant instructions before early-cse has a chance to run. It changes the default (canonical-forming) behavior of SimplifyCFG, so we're only doing the sinking transform later in the optimization pipeline. Differential Revision: https://reviews.llvm.org/D38566 llvm-svn: 320749
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-1410-146/+73
| | | | | | | | | | | | | | Rather than adding more bits to express every MMO flag you could want, just directly use the MMO flags. Also fixes using a bunch of bool arguments to getMemIntrinsicNode. On AMDGPU, buffer and image intrinsics should always have MODereferencable set, but currently there is no way to do that directly during the initial intrinsic lowering. llvm-svn: 320746
* [Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek2017-12-145-7/+111
| | | | llvm-svn: 320744
* [WebAssembly] Add support for init functions linking metadataSam Clegg2017-12-142-1/+27
| | | | | | | | | | | | | | | Summary: This change lays the groundwork lowering of @llvm.global_ctors and @llvm.global_dtors for the wasm object format. Some parts of this patch are subset of: https://reviews.llvm.org/D40759 See https://github.com/WebAssembly/tool-conventions/issues/25 Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41208 llvm-svn: 320742
* [SLPVectorizer] Don't ignore scalar extraction instructions of aggregate valueGuozhi Wei2017-12-141-3/+7
| | | | | | | | | In SLPVectorizer, the vector build instructions (insertvalue for aggregate type) is passed to BoUpSLP.buildTree, it is treated as UserIgnoreList, so later in cost estimation, the cost of these instructions are not counted. For aggregate value, later usage are more likely to be done in scalar registers, either used as individual scalars or used as a whole for function call or return value. Ignore scalar extraction instructions may cause too aggressive vectorization for aggregate values, and slow down performance. So for vectorization of aggregate value, the scalar extraction instructions are required in cost estimation. Differential Revision: https://reviews.llvm.org/D41139 llvm-svn: 320736
* Add MVT::v128i1, NFCKrzysztof Parzyszek2017-12-141-0/+2
| | | | | | | Hexagon HVX has type v128i8, comparing two vectors of that type will produce v128i1 types in SelectionDAG. llvm-svn: 320732
* [MC] Allow .file directives to be out-of-orderPaul Robinson2017-12-141-1/+2
| | | | llvm-svn: 320727
* [X86] Don't zero the upper bits of the k-register before extracting a single ↵Craig Topper2017-12-141-6/+3
| | | | | | | | bit from a vXi1. This doesn't match the semantics of the extract_vector_elt operation. Nothing downstream knows the bits were zeroed so they still get masked or sign extended after the extrat anyway. llvm-svn: 320723
* [Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek2017-12-145-69/+24
| | | | | | HVX does not support operations on 64-bit integers. llvm-svn: 320722
* [COFF] Teach LLD to use the COFF .debug$H section.Zachary Turner2017-12-142-13/+116
| | | | | | | | | | | | This adds the /DEBUG:GHASH option to LLD which will look for the existence of .debug$H sections in linker inputs and use them to accelerate type merging. The clang-cl side has already been added, so this completes the work necessary to begin experimenting with this feature. Differential Revision: https://reviews.llvm.org/D40980 llvm-svn: 320719
* [ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.Geoff Berry2017-12-141-1/+3
| | | | | | Fixes expensive-check ARM buildbot failure. llvm-svn: 320718
* Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-143-19/+11
| | | | | | This commit might have caused regression on ppc64. Revert it to verify that. llvm-svn: 320712
* Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
* [mips] Add partial support for R6 in the long branch passSimon Dardis2017-12-141-46/+116
| | | | | | | | | | | | | | | | | | | | MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
* [ScalarEvolution] Fix base condition in isNormalAddRecPHI.Bjorn Pettersson2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The function is meant to recurse until it comes upon the phi it's looking for. However, with the current condition, it will recurse until it finds anything _but_ the phi. The function will even fail for simple cases like: %i = phi i32 [ %inc, %loop ], ... ... %inc = add i32 %i, 1 because the base condition will not happen when the phi is recursed to, and the recursion will end with a 'false' result since the previous instruction is a phi. Reviewers: sanjoy, atrick Reviewed By: sanjoy Subscribers: Ka-Ka, bjope, llvm-commits Committing on behalf of: Bevin Hansson (bevinh) Differential Revision: https://reviews.llvm.org/D40946 llvm-svn: 320700
* [InlineCost] Tracking Values through PHI NodesHaicheng Wu2017-12-141-6/+138
| | | | | | | | | | | | This patch fix this FIXME in visitPHI() FIXME: We should potentially be tracking values through phi nodes, especially when they collapse to a single value due to deleted CFG edges during inlining. Differential Revision: https://reviews.llvm.org/D38594 llvm-svn: 320699
* Revert "[DAGCombine] Move AND nodes to multiple load leaves"Benjamin Kramer2017-12-141-124/+0
| | | | | | This reverts commit r320679. Causes miscompiles. llvm-svn: 320698
* Any Target Asm comments should start from MachineInstr::TAsmComments value.Andrew V. Tischenko2017-12-141-1/+4
| | | | llvm-svn: 320693
* [AVX512] Adding support for load truncate store of I1Michael Zuckerman2017-12-141-0/+3
| | | | | | | | | | store operation on a truncated memory (load) of vXi1 is poorly supported by LLVM and most of the time end with an assertion. This patch fixes this issue. Differential Revision: https://reviews.llvm.org/D39547 Change-Id: Ida5523dd09c1ad384acc0a27e9e59273d28cbdc9 llvm-svn: 320691
* [PM][InstCombine] fixing omission of AliasAnalysis in new-pass-manager's ↵Fedor Sergeev2017-12-141-2/+3
| | | | | | | | | | | | | | | | | | version of InstCombine Summary: Passing AliasAnalysis results instead of nullptr appears to work just fine. A couple new-pass-manager tests updated to align with new order of analyses. Reviewers: chandlerc, spatel, craig.topper Reviewed By: chandlerc Subscribers: mehdi_amini, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D41203 llvm-svn: 320687
* Remove redundant includes from lib/Target/AArch64.Fedor Sergeev2017-12-141-1/+0
| | | | llvm-svn: 320686
* [CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-5/+3
| | | | | | | | | Work towards the unification of MIR and debug output by printing `<mcsymbol sym>` instead of `<MCSym=sym>`. Only debug syntax is affected. llvm-svn: 320685
* [CodeGen] Move printing MO_Metadata operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-142-6/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320684
* [CodeGen] Print live-out register lists as liveout(...) in both MIR and ↵Francis Visoiu Mistrih2017-12-142-18/+20
| | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `liveout(...)` instead of `<regliveout>`. Only debug syntax is affected. llvm-svn: 320683
* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-146-95/+92
| | | | | | | | | | | | Work towards the unification of MIR and debug output by printing `@foo` instead of `<ga:@foo>`. Also print target flags in the MIR format since most of them are used on global address operands. Only debug syntax is affected. llvm-svn: 320682
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