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* SwitchInst cosmetics: renamed "Hash" method to "hash"Stepan Dyatkovskiy2012-05-142-2/+2
| | | | llvm-svn: 156757
* Use ArrayRef instead of an explicit vector type.Bill Wendling2012-05-141-2/+1
| | | | llvm-svn: 156755
* Hexagon: Initialize TBB to 0.Benjamin Kramer2012-05-131-0/+1
| | | | | | Found by valgrind. llvm-svn: 156744
* Fix spacing after if.Benjamin Kramer2012-05-121-6/+5
| | | | llvm-svn: 156716
* Add support for the .rept directive. Patch by Vladmir Sorokin. I added supportRafael Espindola2012-05-121-0/+91
| | | | | | for nesting. llvm-svn: 156714
* ELF: Add support for the asm .version directive.Benjamin Kramer2012-05-121-0/+28
| | | | llvm-svn: 156712
* AsmParser: Add support for the .purgem directive.Benjamin Kramer2012-05-121-0/+23
| | | | | | Based on a patch by Team PaX. llvm-svn: 156709
* AsmParser: Give a nice error message for .code16gcc, which is currently ↵Benjamin Kramer2012-05-121-1/+1
| | | | | | | | unsupported. Patch by Team PaX! llvm-svn: 156708
* AsmParser: ignore the .extern directive.Benjamin Kramer2012-05-121-0/+4
| | | | llvm-svn: 156707
* AsmParser: Add support for .ifc and .ifnc directives.Benjamin Kramer2012-05-121-0/+54
| | | | | | Based on a patch from PaX Team. llvm-svn: 156706
* AsmParser: Add support for .ifb and .ifnb directives.Benjamin Kramer2012-05-121-0/+29
| | | | | | Based on a patch from PaX Team. llvm-svn: 156705
* Recommited r156374 with critical fixes in BitcodeReader/Writer:Stepan Dyatkovskiy2012-05-123-38/+157
| | | | | | | | Ordinary patch for PR1255. Added new case-ranges orientated methods for adding/removing cases in SwitchInst. After this patch cases will internally representated as ConstantArray-s instead of ConstantInt, externally cases wrapped within the ConstantRangesSet object. Old methods of SwitchInst are also works well, but marked as deprecated. So on this stage we have no side effects except that I added support for case ranges in BitcodeReader/Writer, of course test for Bitcode is also added. Old "switch" format is also supported. llvm-svn: 156704
* Teach Function::hasAddressTaken that BlockAddress doesn't really takeJay Foad2012-05-122-1/+6
| | | | | | the address of a function. llvm-svn: 156703
* Make sure new value jump is enabled for Hexagon V5 as well.Sirish Pande2012-05-121-10/+27
| | | | llvm-svn: 156700
* Support for Hexagon feature, New Value Jump.Sirish Pande2012-05-127-2/+682
| | | | llvm-svn: 156698
* Remove MipsEmitGPRestore.cpp.Akira Hatanaka2012-05-123-99/+0
| | | | llvm-svn: 156696
* Delete all functions that are no longer needed in MipsFunctionInfo, includingAkira Hatanaka2012-05-122-15/+1
| | | | | | | | | the ones that get or set the frame index for the $gp save slot. Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns GP. This function should always return a virtual register. llvm-svn: 156695
* Stop reserving register $gp. Do not call isGPFI to check whether a frame objectAkira Hatanaka2012-05-121-8/+1
| | | | | | is the $gp save slot. llvm-svn: 156694
* Do not add the pass which restores $gp after every function call.Akira Hatanaka2012-05-121-9/+0
| | | | llvm-svn: 156693
* Make the following changes in MipsISelLowering.cpp:Akira Hatanaka2012-05-121-8/+8
| | | | | | | | | - Stop creating stack frame objects needed for saving $gp. - Insert a node that copies the global pointer register to register $gp before the call node. This will ensure $gp is valid at the entry of the called function. llvm-svn: 156692
* Make the following changes in MipsFrameLowering.cpp:Akira Hatanaka2012-05-121-32/+3
| | | | | | | | - Stop emitting instructions needed to initialize the global pointer register. - Stop emitting .cprestore directive. - Do not take into account the $gp save slot when computing stack size. llvm-svn: 156691
* Make the following changes in MipsAsmPrinter.cpp:Akira Hatanaka2012-05-123-31/+11
| | | | | | | | | - Remove code which lowers pseudo SETGP01. - Fix LowerSETGP01. The first two of the three instructions that are emitted to initialize the global pointer register now use register $2. - Stop emitting .cpload directive. llvm-svn: 156689
* Hoist simpler checks above llvm::PointerMayBeCaptured. No functional change ↵Chad Rosier2012-05-121-4/+6
| | | | | | intended. llvm-svn: 156687
* Don't look for empty live ranges in the unions.Jakob Stoklund Olesen2012-05-121-1/+4
| | | | | | | | | Empty live ranges represent undef and still get allocated, but they won't appear in LiveIntervalUnions. Patch by Patrik Hägglund! llvm-svn: 156685
* Insert instructions to the entry basic block which initializes the globalAkira Hatanaka2012-05-121-35/+52
| | | | | | | | | | | | | | | | | | pointer register. This is the first of the series of patches which clean up the way global pointer register is used. The patches will make the following improvements: - Make $gp an allocatable temporary register rather than reserving it. - Use a virtual register as the global pointer register and let the register allocator decide which register to assign to it or whether spill/reloads are needed. - Make sure $gp is valid at the entry of a called function, which is necessary for functions using lazy binding. - Remove the need for emitting .cprestore and .cpload directives. llvm-svn: 156671
* Do not replace operands of pseudo instructions with register $zero.Akira Hatanaka2012-05-111-1/+2
| | | | llvm-svn: 156663
* Revert 156658.Chad Rosier2012-05-111-2/+1
| | | | llvm-svn: 156662
* [fast-isel] Fast-isel doesn't use the expect intrinsic.Chad Rosier2012-05-111-1/+2
| | | | llvm-svn: 156658
* [Support/StringRef] Add find_last_not_of and {r,l,}trim.Michael J. Spencer2012-05-111-0/+26
| | | | llvm-svn: 156652
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-111-0/+4
| | | | llvm-svn: 156646
* Updated instruction table due to addded intrinsics.Brendon Cahoon2012-05-111-1880/+1943
| | | | llvm-svn: 156644
* Remove warnings from HexagonVLIWPacketizer.Sirish Pande2012-05-111-3/+3
| | | | llvm-svn: 156636
* Hexagon constant extender support.Brendon Cahoon2012-05-1115-339/+3626
| | | | | | Patch by Jyotsna Verma. llvm-svn: 156634
* Typo.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156633
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. ↵Chad Rosier2012-05-111-12/+2
| | | | | | Minor cleanup. llvm-svn: 156632
* Hexagon V5 intrinsics support.Sirish Pande2012-05-113-615/+1061
| | | | llvm-svn: 156631
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-111-4/+21
| | | | | | | | retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 llvm-svn: 156628
* objectsize: add a few more tests and fix a bugNuno Lopes2012-05-111-1/+1
| | | | llvm-svn: 156625
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
| | | | | | | | to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 llvm-svn: 156622
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156621
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
| | | | llvm-svn: 156620
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-114-130/+350
| | | | llvm-svn: 156615
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-114-16/+35
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-112-0/+5
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-112-3/+9
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
| | | | llvm-svn: 156603
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-1112-35/+35
| | | | llvm-svn: 156602
* Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman2012-05-111-1/+1
| | | | llvm-svn: 156600
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-112-27/+128
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-113-0/+8
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
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