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* It doesn't make sense to move symbol relocations to section relocations whenEli Bendersky2012-04-302-26/+27
| | | | | | | | | relocations are resolved. It's much more reasonable to do this decision when relocations are just being added - we have all the information at that point. Also a bit of renaming and extra comments to clarify extensions. llvm-svn: 155819
* Just mark the sign bit as known zero, rather than any other irrelevant bitsDuncan Sands2012-04-301-1/+1
| | | | | | known zero in the LHS. Fixes PR12541. llvm-svn: 155818
* Second attempt at PR12573:Bill Wendling2012-04-302-13/+28
| | | | | | | | | | | Allow the "SplitCriticalEdge" function to split the edge to a landing pad. If the pass is *sure* that it thinks it knows what it's doing, then it may go ahead and specify that the landing pad can have its critical edge split. The loop unswitch pass is one of these passes. It will split the critical edges of all edges coming from a loop to a landing pad not within the loop. Doing so will retain important loop analysis information, such as loop simplify. llvm-svn: 155817
* Use an ArrayRef instead of explicit vector type.Bill Wendling2012-04-301-8/+5
| | | | llvm-svn: 155816
* Code cleanup in RuntimeDyld:Eli Bendersky2012-04-304-72/+95
| | | | | | | | | - Add comments - Change field names to be more reasonable - Fix indentation and naming to conform to coding conventions - Remove unnecessary includes / replace them by forward declatations llvm-svn: 155815
* Remove hack from r154987. The problem persists even with it, so it's not ↵Bill Wendling2012-04-301-11/+1
| | | | | | even a good hack. llvm-svn: 155813
* No need to normalize index before calling Extract128BitVectorCraig Topper2012-04-301-12/+11
| | | | llvm-svn: 155811
* Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT ↵Pete Cooper2012-04-302-97/+534
| | | | | | emitter. Needs some major refactoring as these two code emitters are almost identical llvm-svn: 155810
* Make sure HoistInsertPosition finds a position that is dominated by allRafael Espindola2012-04-301-1/+1
| | | | | | inputs. llvm-svn: 155809
* Remove unneeded casts. No functionality change.Jakub Staszak2012-04-291-11/+11
| | | | llvm-svn: 155800
* Simplify code a bit. No functional change intended.Craig Topper2012-04-291-4/+3
| | | | llvm-svn: 155798
* Update the documentation of CellSPU, in case it gets removed in 3.1.Kalle Raiskila2012-04-291-0/+14
| | | | llvm-svn: 155797
* RegisterPressure: ArrayRefize some functions for better readability. No ↵Benjamin Kramer2012-04-292-38/+40
| | | | | | functionality change. llvm-svn: 155795
* Fix some formatting, grammar and style issues and add a couple of missing ↵Eli Bendersky2012-04-295-28/+30
| | | | | | comments. llvm-svn: 155793
* Don't update spill weights when joining intervals.Jakob Stoklund Olesen2012-04-281-25/+0
| | | | | | We don't compute spill weights until after coalescing anyway. llvm-svn: 155766
* Spring cleaning - Delete dead code.Jakob Stoklund Olesen2012-04-281-12/+0
| | | | llvm-svn: 155765
* Fix a problem with blocks that need to be split twice.Jakob Stoklund Olesen2012-04-281-3/+5
| | | | | | | | | The code could search past the end of the basic block when there was already a constant pool entry after the block. Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c llvm-svn: 155753
* Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-281-26/+58
| | | | | | | | | | This time, also fix the caller of AddGlue to properly handle incomplete chains. AddGlue had failure modes, but shamefully hid them from its caller. It's luck ran out. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155749
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-272-2/+22
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 llvm-svn: 155748
* ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach2012-04-272-3/+3
| | | | | | Make the operand order of the instruction match that of the asm syntax. llvm-svn: 155747
* Revert r155745Derek Schuff2012-04-271-2/+0
| | | | llvm-svn: 155746
* Fix fastcc structure return with fast-isel on x86-32Derek Schuff2012-04-271-0/+2
| | | | | | | | | | | | On x86-32, structure return via sret lets the callee pop the hidden pointer argument off the stack, which the caller then re-pushes. However if the calling convention is fastcc, then a register is used instead, and the caller should not adjust the stack. This is implemented with a check of IsTailCallConvention X86TargetLowering::LowerCall but is now checked properly in X86FastISel::DoSelectCall. llvm-svn: 155745
* Track worst case alignment padding more accurately.Jakob Stoklund Olesen2012-04-271-42/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, ARMConstantIslandPass would conservatively compute the address of an aligned basic block as: RoundUpToAlignment(Offset + UnknownPadding) This worked fine for the layout algorithm itself, but it could fool the verify() function because it accounts for alignment padding twice: Once when adding the worst case UnknownPadding, and again by rounding up the fictional block offset. This meant that when optimizeThumb2Instructions would shrink an instruction, the conservative distance estimate could grow. That shouldn't be possible since the woorst case alignment padding wss already included. This patch drops the use of RoundUpToAlignment, and depends only on worst case padding to compute conservative block offsets. This has the weird effect that the computed offset for an aligned block may not be aligned. The important difference is that shrinking an instruction can never cause the estimated distance between two instructions to grow. The estimated distance is always larger than the real distance that only the assembler knows. <rdar://problem/11339352> llvm-svn: 155744
* Temporarily revert r155668: Fix the SD scheduler to avoid gluing.Andrew Trick2012-04-271-4/+2
| | | | | | This definitely caused regression with ARM -mno-thumb. llvm-svn: 155743
* Use 'unsigned' instead of 'int' in several places when retrieving number of ↵Craig Topper2012-04-271-12/+12
| | | | | | vector elements. llvm-svn: 155742
* Add x86-specific DAG combine to simplify:Chad Rosier2012-04-271-0/+28
| | | | | | | | | | | | | | | | | | | | | x == -y --> x+y == 0 x != -y --> x+y != 0 On x86, the generated code goes from negl %esi cmpl %esi, %edi je .LBB0_2 to addl %esi, %edi je .L4 This case is correctly handled for ARM with "cmn". Patch by Manman Ren. rdar://11245199 PR12545 llvm-svn: 155739
* [Support/YAMLParser] Fix ASan found bugs.Michael J. Spencer2012-04-271-1/+7
| | | | llvm-svn: 155735
* Tidy up spacing.Craig Topper2012-04-271-2/+2
| | | | llvm-svn: 155733
* Don't vectorize target-specific types (ppc_fp128, x86_fp80, etc.).Hal Finkel2012-04-271-0/+6
| | | | | | | | | | Target specific types should not be vectorized. As a practical matter, these types are already register matched (at least in the x86 case), and codegen does not always work correctly (at least in the ppc case, and this is not worth fixing because ppc_fp128 is currently broken and will probably go away soon). llvm-svn: 155729
* Change recurse depth limit to uint32 to fix warning.David Blaikie2012-04-271-1/+1
| | | | llvm-svn: 155727
* Miscellaneous accumulated cleanups.Dan Gohman2012-04-271-71/+57
| | | | llvm-svn: 155725
* Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames2012-04-272-24/+25
| | | | | | <rdar://problem/11325085>. llvm-svn: 155724
* Add an early bailout to IsValueFullyAvailableInBlock from deeply nested blocks.Mon P Wang2012-04-271-3/+12
| | | | | | | The limit is set to an arbitrary 1000 recursion depth to avoid stack overflow issues. <rdar://problem/11286839>. llvm-svn: 155722
* Reapply r155682, making constant folding more consistent, with a fix to workDan Gohman2012-04-272-35/+57
| | | | | | properly with how the code handles all-undef PHI nodes. llvm-svn: 155721
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-1/+1
| | | | llvm-svn: 155720
* X86: Don't emit conditional floating point moves on when targeting ↵Benjamin Kramer2012-04-275-15/+84
| | | | | | | | | | | | | | | pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
* [asan] small optimization: do not emit "x+0" instructions Kostya Serebryany2012-04-271-3/+4
| | | | llvm-svn: 155701
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-273-14/+7
| | | | | | the mask operand in the MCInst. llvm-svn: 155700
* Revert r155682, "Use ConstantExpr::getExtractElement when constant-folding ↵NAKAMURA Takumi2012-04-272-51/+32
| | | | | | | | vectors" It broke stage2 build. stage1/clang sometimes crashed. llvm-svn: 155699
* [tsan] Atomic support for ThreadSanitizer, patch by Dmitry VyukovKostya Serebryany2012-04-271-33/+152
| | | | llvm-svn: 155698
* Implement a bastardized ABI.Evan Cheng2012-04-272-3/+5
| | | | llvm-svn: 155686
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-272-16/+28
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* Use ConstantExpr::getExtractElement when constant-folding vectorsDan Gohman2012-04-272-32/+51
| | | | | | | | | | | | | | | | | | | | | instead of getAggregateElement. This has the advantage of being more consistent and allowing higher-level constant folding to procede even if an inner extract element cannot be folded. Make ConstantFoldInstruction call ConstantFoldConstantExpression on the instruction's operands, making it more consistent with ConstantFoldConstantExpression itself. This makes sure that ConstantExprs get TargetData-aware folding before being handed off as operands for further folding. This causes more expressions to be folded, but due to a known shortcoming in constant folding, this currently has the side effect of stripping a few more nuw and inbounds flags in the non-targetdata side of constant-fold-gep.ll. This is mostly harmless. This fixes rdar://11324230. llvm-svn: 155682
* Break up getProfitableChainIncrement().Jakob Stoklund Olesen2012-04-261-39/+47
| | | | | | | | | | | The required checks are moved to ChainInstruction() itself and the policy decisions are moved to IVChain::isProfitableInc(). Also cache the ExprBase in IVChain to avoid frequent recomputations. No functional change intended. llvm-svn: 155676
* Turn IVChain into a struct.Jakob Stoklund Olesen2012-04-261-19/+42
| | | | | | No functional change intended. llvm-svn: 155675
* Add instcombine patterns for the following transformations:Chad Rosier2012-04-262-0/+19
| | | | | | | | | | (x & y) | (x ^ y) -> x | y (x & y) + (x ^ y) -> x | y Patch by Manman Ren. rdar://10770603 llvm-svn: 155674
* Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-261-3/+5
| | | | | | | | | | | DAGCombine strangeness may result in multiple loads from the same offset. They both may try to glue themselves to another load. We could insist that the redundant loads glue themselves to each other, but the beter fix is to bail out from bad gluing at the time we detect it. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155668
* ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach2012-04-261-1/+2
| | | | | | | | | | The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 llvm-svn: 155659
* Trivial change to set UseLeaForSP flag in addition to togglingPreston Gurd2012-04-261-0/+2
| | | | | | | | the FeatureLeaForSP feature bit when llvm auto detects Intel Atom. Patch by Andy Zhang llvm-svn: 155655
* [Support/YAML] Properly fix unitialized variable warning by inserting aMichael J. Spencer2012-04-261-6/+12
| | | | | | 'REPLACEMENT CHARACTER' (U+FFFD) when getAsInteger fails. llvm-svn: 155653
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