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* [ARM] Minor refactoring. NFC.Chad Rosier2015-10-061-2/+4
| | | | llvm-svn: 249465
* [ARM] Minor refactoring. NFC.Chad Rosier2015-10-061-8/+10
| | | | llvm-svn: 249464
* [ARM] Minor refactoring. NFC.Chad Rosier2015-10-061-9/+8
| | | | llvm-svn: 249463
* [Function] Clean up {prefix,prologue} data routines (NFC)Vedant Kumar2015-10-062-40/+39
| | | | | | | | | | | Factor out some common code used to get+set function prefix/prologue data. This may come in handy if we ever decide to store personality functions in the same way we store prefix/prologue data. Differential Revision: http://reviews.llvm.org/D13120 Reviewed-by: bogner llvm-svn: 249460
* [WinEH] Implement state numbering for CoreCLRJoseph Tremoulet2015-10-062-0/+91
| | | | | | | | | | | | | | | | Summary: Assign one state number per handler/funclet, tracking parent state, handler type, and catch type token. State numbers are arranged such that ancestors have lower state numbers than their descendants. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: pgavlin, AndyAyers, llvm-commits Differential Revision: http://reviews.llvm.org/D13450 llvm-svn: 249457
* [WinEH] Recognize CoreCLR personality functionJoseph Tremoulet2015-10-0610-22/+26
| | | | | | | | | | | | | | | Summary: - Add CoreCLR to if/else ladders and switches as appropriate. - Rename isMSVCEHPersonality to isFuncletEHPersonality to better reflect what it captures. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: pgavlin, AndyAyers, llvm-commits Differential Revision: http://reviews.llvm.org/D13449 llvm-svn: 249455
* [ARM] Minor refactoring to improve readability. NFC.Chad Rosier2015-10-061-13/+14
| | | | llvm-svn: 249454
* Extend known bits to understand @llvm.bswapPhilip Reames2015-10-061-0/+6
| | | | | | | | | | This is a cleaned up patch from the one written by John Regehr based on the findings of the Souper superoptimizer. When writing tests, I was surprised to find that instsimplify apparently doesn't know how to collapse bit test sequences based purely on known bits. This required me to split my tests across both instsimplify and instcombine. Differential Revision: http://reviews.llvm.org/D13250 llvm-svn: 249453
* Fix pr25040 - Handle vectors of i1s in recently added implication codePhilip Reames2015-10-061-4/+11
| | | | | | | | As mentioned in the bug, I'd missed the presence of a getScalarType in the caller of the new implies method. As a result, when we ended up with a implication over two vectors, we'd trip an assert and crash. Differential Revision: http://reviews.llvm.org/D13441 llvm-svn: 249442
* [Hexagon] Remove ZeroOrMore from option flagsKrzysztof Parzyszek2015-10-061-4/+3
| | | | llvm-svn: 249438
* This patch builds on top of D13378 to handle constant condition.Mehdi Amini2015-10-061-0/+5
| | | | | | | | | | | | | | | | | | | | With this patch, clang -O3 optimizes correctly providing > 1000x speedup on this artificial benchmark): for (a=0; a<n; a++) for (b=0; b<n; b++) for (c=0; c<n; c++) for (d=0; d<n; d++) for (e=0; e<n; e++) for (f=0; f<n; f++) x++; From test-suite/SingleSource/Benchmarks/Shootout/nestedloop.c Reviewers: sanjoyd Differential Revision: http://reviews.llvm.org/D13390 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 249431
* AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcpTom Stellard2015-10-065-25/+56
| | | | | | | | | | | | | | Summary: The assembly printing of these is still missing the encoding size suffix, but this will be fixed in a later commit. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13436 llvm-svn: 249424
* [Hexagon] Add an early if-conversion passKrzysztof Parzyszek2015-10-064-17/+1149
| | | | llvm-svn: 249423
* [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backendDaniel Sanders2015-10-061-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes 7 tests during fast LLVM test-suite run: * MultiSource/Benchmarks/McCat/18-imp/imp * MultiSource/Applications/oggenc/oggenc * MultiSource/Benchmarks/MallocBench/gs/gs * MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan * MultiSource/Benchmarks/VersaBench/beamformer/beamformer * MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame * MultiSource/Benchmarks/Bullet/bullet Error message was in the form of: fatal error: error in backend: Cannot select: 0x95c3288: f32 = fsqrt 0x95c0190 [ORD=9] [ID=18] 0x95c0190: f32 = fadd 0x95bef30, 0x95c4d00 [ORD=8] [ID=17] 0x95bef30: f32 = fmul 0x95c4988, 0x95c4988 [ORD=5] [ID=16] ... There was problem with selecting sqrt instruction in LLVM backend. To fix the issue changes are made in TableGen definition for sqrt instruction in MipsInstrFPU.td and new test file sqrt.ll is added to LLVM regression tests. Patch by Zlatko Buljan Reviewers: zoran.jovanovic, hvarga, dsanders Subscribers: llvm-commits, petarj Differential Revision: http://reviews.llvm.org/D13235 llvm-svn: 249416
* Revert r249123 - [mips][microMIPS] Fix an issue with selecting sqrt ↵Daniel Sanders2015-10-061-2/+5
| | | | | | | | instruction in LLVM backend The author was not credited and most of the commit message is missing. Will re-commit with this fixed. llvm-svn: 249415
* [EarlyCSE] Constify ParseMemoryInst methods (NFC).Arnaud A. de Grandmaison2015-10-061-9/+9
| | | | llvm-svn: 249400
* Make sure the CastInst is valid before trying to create itFilipe Cabecinhas2015-10-061-1/+4
| | | | | | Bug found with afl-fuzz. llvm-svn: 249396
* [InstCombine] Teach SimplifyDemandedVectorElts how to handle ConstantVector ↵Andrea Di Biagio2015-10-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | select masks with ConstantExpr elements (PR24922) If the mask of a select instruction is a ConstantVector, method SimplifyDemandedVectorElts iterates over the mask elements to identify which values are selected from the select inputs. Before this patch, method SimplifyDemandedVectorElts always used method Constant::isNullValue() to check if a value in the mask was zero. Unfortunately that method always returns false when called on a ConstantExpr. This patch fixes the problem in SimplifyDemandedVectorElts by adding an explicit check for ConstantExpr values. Now, if a value in the mask is a ConstantExpr, we avoid calling isNullValue() on it. Fixes PR24922. Differential Revision: http://reviews.llvm.org/D13219 llvm-svn: 249390
* [TwoAddressInstructionPass] When looking for a 3 addr conversion after ↵Craig Topper2015-10-061-0/+7
| | | | | | commuting, make sure regB has been updated to take into account the commute. llvm-svn: 249378
* [bpf] Avoid extra pointer arithmetic for stack accessAlexei Starovoitov2015-10-063-7/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For the program like below struct key_t { int pid; char name[16]; }; extern void test1(char *); int test() { struct key_t key = {}; test1(key.name); return 0; } For key.name, the llc/bpf may generate the below code: R1 = R10 // R10 is the frame pointer R1 += -24 // framepointer adjustment R1 |= 4 // R1 is then used as the first parameter of test1 OR operation is not recognized by in-kernel verifier. This patch introduces an intermediate FI_ri instruction and generates the following code that can be properly verified: R1 = R10 R1 += -20 Patch by Yonghong Song <yhs@plumgrid.com> llvm-svn: 249371
* [X86] Teach constant hoisting that ANDs with 64-bit immediates in the range ↵Craig Topper2015-10-061-1/+7
| | | | | | | | 0x80000000-0xffffffff can be handled cheaply and don't need to be hoisted. Most importantly, this keeps constant hoisting from preventing instruction selections ability to turn an AND with 0xffffffff into a move into a 32-bit subregister. llvm-svn: 249370
* [X86] Remove unnecessary AddComplexity directive. The instruction is already ↵Craig Topper2015-10-061-1/+0
| | | | | | wrapped in the equivalent earlier. NFC llvm-svn: 249369
* [WebAssembly] Switch to a more traditional assembly syntaxDan Gohman2015-10-064-144/+113
| | | | | | | | | | | This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
* Move helper classes into an anonymous namespace. NFC.Benjamin Kramer2015-10-051-0/+2
| | | | llvm-svn: 249356
* Remove AutoFDO profile handling for GCC's LIPO. NFC.Diego Novillo2015-10-051-22/+0
| | | | | | | | Given the work we are doing on ThinLTO, we will never need to support module groups and working sets in GCC's implementation of LIPO. These are currently dead code, and will continue to be so. llvm-svn: 249351
* [WinEH] Update CATCHRET's operand to match its successorDavid Majnemer2015-10-053-9/+28
| | | | | | | | | | | | The CATCHRET operand did not match the MachineFunction's CFG. This mismatch happened because FrameLowering created a new MachineBasicBlock and updated the CFG but forgot to update the CATCHRET operand. Let's make sure this doesn't happen again by strengthing the funclet membership analysis: it can now reason about the membership of all basic blocks, not just those inside of funclets. llvm-svn: 249344
* Simplify code. No functionality change.Jakub Staszak2015-10-051-9/+2
| | | | llvm-svn: 249335
* [msan] Correct a typo in poison stack pattern command line description.Evgeniy Stepanov2015-10-051-1/+1
| | | | | | Patch by Jon Eyolfson. llvm-svn: 249331
* AMDGPU/SI: Add a helper for creating aliases for the _e32 instructionsTom Stellard2015-10-051-11/+49
| | | | | | | | | | | | | | | | | | Summary: We are currently only using these aliases for VOPC instructions, but this helper will make it easier to use them everywhere. These aliases allow for the automatic matching of instructions with forced 32-bit encoding. Eventually, we should be able to remove the custom C++ logic we have for this in the assembler. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13396 llvm-svn: 249330
* MergeFunctions: Clear GlobalNumbers ValueMapArnold Schwaighofer2015-10-051-0/+4
| | | | | | | | | | | Otherwise, the map will observe changes as long as MergeFunctions is alive. This is bad because follow-up passes could replace-all-uses-with on the key of an entry in the map. The value handle callback of ValueMap however asserts that the key type matches. rdar://22971893 llvm-svn: 249327
* [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM.Scott Douglass2015-10-058-30/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were previously codegen'ing memcpy as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achieving better codegen is to create MEMCPY pseudo instructions, attach scratch virtual registers to them and then, post register allocation, expand the MEMCPYs into LDM/STM pairs using the scratch registers. The register allocator will have picked arbitrary registers which we sort when expanding the MEMCPY. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. Fixes PR9199 and PR23768. [This is based on Peter Collingbourne's r238473 which was reverted.] Differential Revision: http://reviews.llvm.org/D13239 Change-Id: I727543c2e94136e0f80b8e22d5642d7b9ee5b458 Author: Peter Collingbourne <peter@pcc.me.uk> llvm-svn: 249322
* [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructionsZoran Jovanovic2015-10-055-5/+82
| | | | | | Differential Revision: http://reviews.llvm.org/D11219 llvm-svn: 249317
* [MC layer][AArch64] llvm-mc accepts 4-bit immediate values forAlexandros Lamprineas2015-10-055-13/+87
| | | | | | | | | "msr pan, #imm", while only 1-bit immediate values should be valid. Changed encoding and decoding for msr pstate instructions. Differential Revision: http://reviews.llvm.org/D13011 llvm-svn: 249313
* [mips] Changed the way symbols are handled in dla and la instructions to ↵Daniel Sanders2015-10-051-12/+9
| | | | | | | | | | | | | | | | | | | | | allow simple expressions. Summary: An instruction like "(d)la $5, symbol+8" previously would have crashed the assembler as it contains an expression. This is now fixed. A few tests cases have also been changed to reflect these changes, however these should only be syntax changes. Some new test cases have also been added. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12760 llvm-svn: 249311
* [Support] Add a version of fs::make_absolute with a custom CWD.Benjamin Kramer2015-10-051-2/+15
| | | | | | This will be used soon from clang. llvm-svn: 249309
* Fix pr24486.Rafael Espindola2015-10-0521-70/+85
| | | | | | | | | | | | | | | | | | This extends the work done in r233995 so that now getFragment (in addition to getSection) also works for variable symbols. With that the existing logic to decide if a-b can be computed works even if a or b are variables. Given that, the expression evaluation can avoid expanding variables as aggressively and that in turn lets the relocation code see the original variable. In order for this to work with the asm streamer, there is now a dummy fragment per section. It is used to assign a section to a symbol when no other fragment exists. This patch is a joint work by Maxim Ostapenko andy myself. llvm-svn: 249303
* [SelectionDAGBuilder] Remove dead codeDavid Majnemer2015-10-041-1/+1
| | | | | | We already check for LandingPadInst two lines above. llvm-svn: 249280
* Remove unused private field introduced by r249270.Teresa Johnson2015-10-041-5/+2
| | | | llvm-svn: 249277
* Support for function summary index bitcode sections and files.Teresa Johnson2015-10-047-41/+1077
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bitcode format is described in this document: https://drive.google.com/file/d/0B036uwnWM6RWdnBLakxmeDdOeXc/view For more info on ThinLTO see: https://sites.google.com/site/llvmthinlto The first customer is ThinLTO, however the data structures are designed and named more generally based on prior feedback. There are a few comments regarding how certain interfaces are used by ThinLTO, and the options added here to gold currently have ThinLTO-specific names as the behavior they provoke is currently ThinLTO-specific. This patch includes support for generating per-module function indexes, the combined index file via the gold plugin, and several tests (more are included with the associated clang patch D11908). Reviewers: dexonsmith, davidxl, joker.eph Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13107 llvm-svn: 249270
* [SPARCv9] Add support for the rdpr/wrpr instructions.Joerg Sonnenberger2015-10-044-0/+131
| | | | llvm-svn: 249262
* AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.Igor Breger2015-10-044-61/+102
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12690 llvm-svn: 249261
* [WinEH] Permit branch folding in the face of funcletsDavid Majnemer2015-10-044-84/+135
| | | | | | | | Track which basic blocks belong to which funclets. Permit branch folding to fire but only if it can prove that doing so will not cause code in one funclet to be reused in another. llvm-svn: 249257
* Fix typo in READMEJeroen Ketema2015-10-041-1/+1
| | | | llvm-svn: 249253
* [DAGCombiner] Generalize FADD constant combines to work with vectorsSimon Pilgrim2015-10-031-16/+17
| | | | | | | | Updated the FADD combines to work with vectors as well as scalars. Differential Revision: http://reviews.llvm.org/D13416 llvm-svn: 249251
* include equal sign in debug equations; NFCSanjay Patel2015-10-031-2/+2
| | | | llvm-svn: 249248
* [X86] Lower SEXTLOAD using SIGN_EXTEND_VECTOR_INREG. NCI.Simon Pilgrim2015-10-031-22/+5
| | | | | | The custom lowering in LowerExtendedLoad is doing the equivalent shuffle, so make use of existing lowering code to reduce duplication. llvm-svn: 249243
* Move registerSection out of line and reduce #includes. NFC.Rafael Espindola2015-10-031-0/+8
| | | | llvm-svn: 249241
* [DAGCombiner] Merge SIGN_EXTEND_INREG vector constant folding methods. NCI.Simon Pilgrim2015-10-032-26/+6
| | | | | | | | | | visitSIGN_EXTEND_INREG calls SelectionDAG::getNode to constant fold scalar constants but handles vector constants itself, despite getNode being capable of dealing with them. This required a minor change to the getNode implementation to actually deal with cases where the scalars of a BUILD_VECTOR were wider integers than the vector type - which was the only extra ability of the visitSIGN_EXTEND_INREG implementation. No codegen intended and all existing tests remain the same. llvm-svn: 249236
* [libFuzzer] trying to fix at-exit hangKostya Serebryany2015-10-031-1/+1
| | | | llvm-svn: 249231
* [WebAssembly] Implement the remaining conversion operations.Dan Gohman2015-10-031-31/+54
| | | | | | | This is a temporary assembly syntax that will likely evolve along with broader upcoming syntax changes. llvm-svn: 249225
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