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* [mips][mips64r6] Add bc[12](eq|ne)zDaniel Sanders2014-05-213-4/+75
| | | | | | | | | | | | Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
* [asan] Fix x86-32 asm instrumentation to preserve flags.Evgeniy Stepanov2014-05-211-2/+1
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 209280
* MC: mark COFF .drectve section as REMOVESaleem Abdulrasool2014-05-211-1/+1
| | | | | | | | | The .drectve section should be marked as IMAGE_SCN_LNK_REMOVE. This matches what the MSVC toolchain does and accurately reflects that this section should not be emitted into the final binary. This section is merely information for the linker, comprising of additional linker directives. llvm-svn: 209273
* [modules] Add module maps for LLVM. These are not quite ready for prime-timeRichard Smith2014-05-216-0/+6
| | | | | | | yet, but only a few more Clang patches need to land. (I have 'ninja check' passing locally.) llvm-svn: 209269
* ARM: correct bundle generation for MOV32T relocationsSaleem Abdulrasool2014-05-211-7/+3
| | | | | | | | | | | | | | | | | | | | | | | Although the previous code would construct a bundle and add the correct elements to it, it would not finalise the bundle. This resulted in the InternalRead markers not being added to the MachineOperands nor, more importantly, the externally visible defs to the bundle itself. So, although the bundle was not exposing the def, the generated code would be correct because there was no optimisations being performed. When optimisations were enabled, the post register allocator would kick in, and the hazard recognizer would reorder operations around the load which would define the value being operated upon. Rather than manually constructing the bundle, simply construct and finalise the bundle via the finaliseBundle call after both MIs have been emitted. This improves the code generation with optimisations where IMAGE_REL_ARM_MOV32T relocations are emitted. The changes to the other tests are the result of the bundle generation preventing the scheduler from hoisting the moves across the loads. The net effect of the generated code is equivalent, but, is much more identical to what is actually being lowered. llvm-svn: 209267
* Move the verbose asm option to be part of the options struct andEric Christopher2014-05-203-27/+7
| | | | | | set appropriately. llvm-svn: 209258
* Update MachOObjectFile::getSymbolAddress so it returns UnknownAddressOrSizeKevin Enderby2014-05-201-3/+17
| | | | | | | | | | | | for undefined symbols, so it matches what COFFObjectFile::getSymbolAddress does. This allows llvm-nm to print spaces instead of 0’s for the value of undefined symbols in Mach-O files. To make this change other uses of MachOObjectFile::getSymbolAddress are updated to handle when the Value is returned as UnknownAddressOrSize. Which is needed to keep two of the ExecutionEngine tests working for example. llvm-svn: 209253
* Revert "DebugInfo: Assume all subprogram DIEs have been created before any ↵David Blaikie2014-05-201-5/+5
| | | | | | | | | | | | | | abstract subprograms are constructed." This reverts commit r209178. This seems to be asserting in an LTO build on some internal Apple buildbots. No upstream reproduction (and I don't have an LLVM-aware gold built right now to reproduce it personally) but it's a small patch & the failure's semi-plausible so I'm going to revert first while I try to reproduce this. llvm-svn: 209251
* [ARM64] PR19792: Fix cycle in DAG after performPostLD1CombineAdam Nemet2014-05-201-1/+6
| | | | | | | | | | | | | | | | | | | Povray and dealII currently assert with "Overran sorted position" in AssignTopologicalOrder. The problem is that performPostLD1Combine can introduce cycles. Consider: (insert_vector_elt (INSERT_SUBREG undef, (load (add %vreg0, Constant<8>), undef), <= A TargetConstant<2>), (load %vreg0, undef), <= B Constant<1>) This is turned into a LD1LANEpost node. However the address in A is not a valid user of the post-incremented address of B in LD1LANEpost. llvm-svn: 209242
* Unbreak the sanitizer buildbots after r209226 due to SROA issue described in ↵David Blaikie2014-05-201-4/+7
| | | | | | | | | | | | | | | http://reviews.llvm.org/D3714 Undecided whether this should include a test case - SROA produces bad dbg.value metadata describing a value for a reference that is actually the value of the thing the reference refers to. For now, loosening the assert lets this not assert, but it's still bogus/wrong output... If someone wants to tell me to add a test, I'm willing/able, just undecided. Hopefully we'll get SROA fixed soon & we can tighten up this assertion again. llvm-svn: 209240
* Move the function and data section flags into the options struct andEric Christopher2014-05-201-15/+6
| | | | | | | | | | make the functions to set them non-static. Move and rename the llvm specific backend options to avoid conflicting with the clang option. Paired with a backend commit to update. llvm-svn: 209238
* Revert r209235 as it broke two tests:Kevin Enderby2014-05-201-10/+2
| | | | | | | | Failing Tests (2): LLVM :: ExecutionEngine/MCJIT/stubs-sm-pic.ll LLVM :: ExecutionEngine/MCJIT/stubs.ll llvm-svn: 209236
* Update MachOObjectFile::getSymbolAddress so it returns UnknownAddressOrSizeKevin Enderby2014-05-201-2/+10
| | | | | | | for undefined symbols. Allowing llvm-nm to print spaces instead of 0’s for the value of undefined symbols in Mach-O files. llvm-svn: 209235
* [LSR] Canonicalize reg1 + ... + regN into reg1 + ... + 1*regN.Quentin Colombet2014-05-201-183/+375
| | | | | | | | | | | | | | This commit introduces a canonical representation for the formulae. Basically, as soon as a formula has more that one base register, the scaled register field is used for one of them. The register put into the scaled register is preferably a loop variant. The commit refactors how the formulae are built in order to produce such representation. This yields a more accurate, but still perfectible, cost model. <rdar://problem/16731508> llvm-svn: 209230
* Fix test breakage introduced in r209223.David Blaikie2014-05-201-1/+2
| | | | | | Oops, broke the broken enum constants again. llvm-svn: 209226
* Rewrite calculateDbgValueHistory to make it (hopefully) more transparent.Alexey Samsonov2014-05-203-122/+142
| | | | | | | | | | | | | | | | | | | | | | This change preserves the original algorithm of generating history for user variables, but makes it more clear. High-level description of algorithm: Scan all the machine basic blocks and machine instructions in the order they are emitted to the object file. Do the following: 1) If we see a DBG_VALUE instruction, add it to the history of the corresponding user variable. Keep track of all user variables, whose locations are described by a register. 2) If we see a regular instruction, look at all the registers it clobbers, and terminate the location range for all variables described by these registers. 3) At the end of the basic block, terminate location ranges for all user variables described by some register. Although this change shouldn't be user-visible (the contents of .debug_loc section should be the same), it changes some internal assumptions about the set of instructions used to track the variable locations. Watching the bots. llvm-svn: 209225
* PR19767: DebugInfo emission of pointer constants.David Blaikie2014-05-201-2/+13
| | | | | | | | | | | | | | | | | In refactoring DwarfUnit::isUnsignedDIType I restricted it to only work on values with signedness (unsigned or signed), asserting on anything else (which did uncover some bugs). But it turns out that we do need to emit constants of signless data, such as pointer constants - only null pointer constants are known to need this so far, but it's conceivable that there might be non-null pointer constants at some point (hardcoded address offsets for device drivers?). This patch just uses 'unsigned' for signless data such as pointer constants. Arguably we could use signless representations (DW_FORM_dataN) instead, allowing a trinary result from isUnsignedDIType (signed, unsigned, signless), but this seems reasonable for now. llvm-svn: 209223
* [PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16ImmediateAdam Nemet2014-05-201-1/+1
| | | | | | | | | | | | | The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64 backend. We matched an immediate offset with STWX8 even though it only supports register offset. The culprit is the complex-pattern predicate, SelectAddrIdx, which decides that if the offset is not ISD::Constant it must be a register. Many thanks to Bill Schmidt for testing this. llvm-svn: 209219
* Clean up language and grammar.Eric Christopher2014-05-207-8/+8
| | | | | | | Based on a patch by jfcaron3@gmail.com! PR19806 llvm-svn: 209216
* Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes ↵Daniel Sanders2014-05-201-124/+117
| | | | | | | | | | | | and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
* TableGen: permit non-leaf ComplexPattern usesTim Northover2014-05-201-6/+8
| | | | | | | | | | | | | | | | | | This allows the results of a ComplexPattern check to be distributed to separate named Operands, instead of the current system where all results must apply (and match perfectly) with a single Operand. For example, if "some_addrmode" is a ComplexPattern producing two results, you can write: def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)), (INST GPR64:$base, imm:$offset)>; This should allow neater instruction definitions in TableGen that don't put all possible aspects of addressing into a single operand, but are still usable with relatively simple C++ CodeGen idioms. llvm-svn: 209206
* Add parentheses to suppress the gcc warning '-Wparentheses'.Simon Atanasyan2014-05-201-2/+2
| | | | | | No functional changes. llvm-svn: 209203
* Legalizer: Make bswap promotion safe for vectors.Benjamin Kramer2014-05-201-2/+2
| | | | llvm-svn: 209202
* [Mips] Add more relocation types and MIPS specific e_flags constants.Simon Atanasyan2014-05-202-0/+21
| | | | llvm-svn: 209201
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-201-1/+4
| | | | llvm-svn: 209200
* TableGen: convert InstAlias's Emit bit to an int.Tim Northover2014-05-202-68/+65
| | | | | | | | | | | | | When multiple aliases overlap, the correct string to print can often be determined purely by considering the InstAlias declarations in some particular order. This allows the user to specify that order manually when desired, without resorting to hacking around with the default lexicographical order on Record instantiation, which is error-prone and ugly. I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4, uxtw". That's only true if Rn is the stack pointer. llvm-svn: 209199
* [X86] Tune LEA usage for SilvermontAlexey Volkov2014-05-207-14/+102
| | | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont in some cases LEA is better to be replaced with ADD instructions: "The rule of thumb for ADDs and LEAs is that it is justified to use LEA with a valid index and/or displacement for non-destructive destination purposes (especially useful for stack offset cases), or to use a SCALE. Otherwise, ADD(s) are preferable." Differential Revision: http://reviews.llvm.org/D3826 llvm-svn: 209198
* [LV][REFACTOR] One more tiny fix for printing debug locations in loop ↵Zinovy Nis2014-05-201-10/+8
| | | | | | | | vectorizer. Now consistent with the remarks emitter. Differential Revision: http://reviews.llvm.org/D3821 llvm-svn: 209197
* Teach isKnownNonNull that a nonnull return is not null. Add a test for this ↵Nick Lewycky2014-05-201-0/+5
| | | | | | case as well as the case of a nonnull attribute (already handled but not tested). llvm-svn: 209193
* DebugInfo: Emit function definitions within their namespace scope.David Blaikie2014-05-201-22/+0
| | | | | | | | This workaround (presumably for ancient GDB) doesn't appear to be required (GDB 7.5 seems to tolerate function definition DIEs in namespace scope just fine). llvm-svn: 209189
* Add 'nonnull', a new parameter and return attribute which indicates that the ↵Nick Lewycky2014-05-208-2/+23
| | | | | | pointer is not null. Instcombine will elide comparisons between these and null. Patch by Luqman Aden! llvm-svn: 209185
* DebugInfo: Assume all subprogram DIEs have been created before any abstract ↵David Blaikie2014-05-191-5/+5
| | | | | | | | | | | | | | subprograms are constructed. Since we visit the whole list of subprograms for each CU at module start, this is clearly true - don't test for the case, just assert it. A few old test cases seemed to have incomplete subprogram lists, but any attempt to reproduce them shows full subprogram lists that even include entities that have been completely inlined and the out of line definition removed. llvm-svn: 209178
* [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.Chad Rosier2014-05-194-60/+152
| | | | | | | Patch by Dave Estes<cestes@codeaurora.org>! PR19761 http://reviews.llvm.org/D3829 llvm-svn: 209176
* Remove unused method declarationMatt Arsenault2014-05-191-1/+0
| | | | llvm-svn: 209174
* DebugInfo: Don't include DW_AT_inline on each abstract definition multiple ↵David Blaikie2014-05-191-1/+0
| | | | | | | | | | | | | | | | | times. When I refactored this in r208636 I accidentally caused this to be added multiple times to each abstract subprogram (not accounting for the deduplicating effect of the InlinedSubprogramDIEs set). This got better in r208798 when the abstract definitions got the attribute added to them at construction time, but still had the redundant copies introduced in r208636. This commit removes those excess DW_AT_inlines and relies solely on the insertion in r208798. llvm-svn: 209166
* DebugInfo: Fix missing inlined_subroutines caused by r208748.David Blaikie2014-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The check in DwarfDebug::constructScopeDIE was meant to consider inlined subroutines as any non-top-level scope that was a subprogram. Instead of checking "not top level scope" it was checking if the /subprogram's/ scope was non-top-level. Fix this and beef up a test case to demonstrate some of the missing inlined_subroutines are no longer missing. In the course of fixing this I also found that r208748 (with this fix) found one /extra/ inlined_subroutine in concrete_out_of_line.ll due to two inlined_subroutines having the same inlinedAt location. The previous implementation was collapsing these into a single inlined subroutine. I'm not sure what the original code was that created this .ll file so I'm not sure if this actually happens in practice today. Since we deliberately include column information to disambiguate two calls on the same line, that may've addressed this bug in the frontend, but it's good to know that workaround isn't necessary for this particular case anymore. llvm-svn: 209165
* Fix typos.Eric Christopher2014-05-191-1/+2
| | | | llvm-svn: 209164
* [ConstantHoisting][X86] Change the cost model to never hoist constants for ↵Juergen Ributzka2014-05-191-2/+13
| | | | | | | | | | | | | | | types larger than i128. Currently the X86 backend doesn't support types larger than i128 very well. For example an i192 multiply will assert in codegen when the 2nd argument is a constant and the constant got hoisted. This fix changes the cost model to never hoist constants for types larger than i128. Once the codegen issues have been resolved, the cost model can be updated to allow also larger types. This is related to <rdar://problem/16954938> llvm-svn: 209162
* [X86] Add ISel patterns to improve the selection of TZCNT and LZCNT.Andrea Di Biagio2014-05-191-0/+81
| | | | | | | | | | Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
* Implement MachOObjectFile::isSectionData() and MachOObjectFile::isSectionBSSKevin Enderby2014-05-191-6/+12
| | | | | | | | so that llvm-size will total up all the sections in the Berkeley format. This allows for rough categorizations for Mach-O sections. And allows the total of llvm-size’s Berkeley and System V formats to be the same. llvm-svn: 209158
* Added more insertps optimizationsFilipe Cabecinhas2014-05-192-11/+72
| | | | | | | | | | | | | | | | | | | | Summary: When inserting an element that's coming from a vector load or a broadcast of a vector (or scalar) load, combine the load into the insertps instruction. Added PerformINSERTPSCombine for the case where we need to fix the load (load of a vector + insertps with a non-zero CountS). Added patterns for the broadcasts. Also added tests for SSE4.1, AVX, and AVX2. Reviewers: delena, nadav, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3581 llvm-svn: 209156
* [RuntimeDyld] Fix x86-64 MachO GOT relocation handling.Lang Hames2014-05-191-2/+7
| | | | | | | | | | | For GOT relocations the addend should modify the offset to the GOT entry, not the value of the entry itself. Teach RuntimeDyldMachO to do The Right Thing here. Fixes <rdar://problem/16961886>. llvm-svn: 209154
* Check the alwaysinline attribute on the call as well as on the caller.Peter Collingbourne2014-05-192-3/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D3815 llvm-svn: 209150
* Use range forMatt Arsenault2014-05-191-4/+1
| | | | llvm-svn: 209147
* reverting r209132Jyotsna Verma2014-05-192-121/+250
| | | | llvm-svn: 209139
* MemoryBuffer: Use GetNativeSystemInfo()Alp Toker2014-05-192-17/+6
| | | | | | | Removes old 4096 byte workaround. This functionality has been available since Windows XP. llvm-svn: 209137
* Revert "Patch for function cloning to inline all blocks whose address is taken"Eric Christopher2014-05-191-106/+34
| | | | | | | | as it was causing build failures in ruby. This reverts commit r207713. llvm-svn: 209135
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-198-64/+144
| | | | llvm-svn: 209134
* Hexagon: Add encoding bits to the mpy instructions.Jyotsna Verma2014-05-192-250/+121
| | | | llvm-svn: 209132
* [mips][mips64r6] Sorted *_ENC, *_DESC classes and testsZoran Jovanovic2014-05-191-117/+124
| | | | | | Differential Revision: http://reviews.llvm.org/D3808 llvm-svn: 209129
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