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* [X86] Fix a bad early out in combineExtInVec that prevented recursive ↵Craig Topper2019-08-051-5/+3
| | | | | | shuffle combining from running with -x86-experimental-vector-widening-legalization. llvm-svn: 367798
* [Attributor][NFC] Create some attributes earlierJohannes Doerfert2019-08-041-6/+6
| | | | llvm-svn: 367793
* [Attributor][NFC] Improve debug outputJohannes Doerfert2019-08-041-1/+2
| | | | llvm-svn: 367792
* [Attributor][Fix] Resolve various liveness issuesJohannes Doerfert2019-08-041-72/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This contains various fixes: - Explicitly determine and return the next noreturn instruction. - If an invoke calls a noreturn function which is not nounwind we keep the unwind destination live. This also means we require an invoke. Though we can still add the unreachable to the normal destination block. - Check if the return instructions are dead after we look for calls to avoid triggering an optimistic fixpoint in the presence of assumed liveness information. - Make the interface work with "const" pointers. - Some simplifications While additional tests are included, full coverage is achieved only with D59978. Reviewers: sstefan1, uenoku Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65701 llvm-svn: 367791
* [Attributor][NFC] Simplify common pattern wrt. fixpointsJohannes Doerfert2019-08-041-70/+41
| | | | | | | | When a fixpoint is indicated the change status is known due to the fixpoint kind. This simplifies a common code pattern by making the connection explicit. llvm-svn: 367790
* [Attributor][NFC] Invalid DerefState is at fixpointJohannes Doerfert2019-08-041-2/+3
| | | | | | | | | | | | | | | | | Summary: If the DerefBytesState (and thereby the DerefState) is invalid, we reached a fixpoint for the whole DerefState as we will not manifest/provide information then. Reviewers: uenoku, sstefan1 Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65586 llvm-svn: 367789
* [TargetLowering][X86] Teach SimplifyDemandedVectorElts to replace the base ↵Craig Topper2019-08-042-17/+9
| | | | | | | | | | | | | | | | | | | | | | | | vector of INSERT_SUBVECTOR with undef if none of the elements are demanded even if the node has other users. Summary: The SimplifyDemandedVectorElts function can replace with undef when no elements are demanded, but due to how it interacts with TargetLoweringOpts, it can only do this when the node has no other users. Remove a now unneeded DAG combine from the X86 backend. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65713 llvm-svn: 367788
* [X86] lowerShuffleAsSpecificZeroOrAnyExtend - use undef PSHUFB mask indices ↵Simon Pilgrim2019-08-041-2/+6
| | | | | | for ANY_EXTEND shuffles llvm-svn: 367784
* Fix signed/unsigned comparison warning. NFC.Simon Pilgrim2019-08-041-1/+1
| | | | llvm-svn: 367783
* [X86] SimplifyMultipleUseDemandedBits - Add target shuffle supportSimon Pilgrim2019-08-041-0/+46
| | | | llvm-svn: 367782
* [ARM] MVE big endian bitcastsDavid Green2019-08-041-0/+45
| | | | | | | | | | | | | | | | | | | | | | This adds big endian MVE patterns for bitcasts. They are defined in llvm as being the same as a store of the existing type and the load into the new. This means that they have to become a VREV between the two types, working in the same way that NEON works in big-endian. This also adds some example tests for bigendian, showing where code is and isn't different. The main difference, especially from a testing perspective is that vectors are passed as v2f64, and so are VREV into and out of call arguments, and the parameters are passed in a v2f64 format. Same happens for inline assembly where the register class is used, so it is VREV to a v16i8. So some of this is probably not correct yet, but it is (mostly) self-consistent and seems to be consistent with how llvm treats vectors. The rest we can hopefully fix later. More details about big endian neon can be found in https://llvm.org/docs/BigEndianNEON.html. Differential Revision: https://reviews.llvm.org/D65581 llvm-svn: 367780
* [llvm-objdump] Re-commit r367284.Michael Pozulp2019-08-042-12/+7
| | | | | | | | | | | | | | | | | | Add warning messages if disassembly + source for problematic inputs Summary: Addresses https://bugs.llvm.org/show_bug.cgi?id=41905 Reviewers: jhenderson, rupprecht, grimar Reviewed By: jhenderson, grimar Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62462 llvm-svn: 367776
* [X86] Consistently use MVT::i8 for the constant operand of BLENDI and ↵Craig Topper2019-08-041-8/+8
| | | | | | | | | INSERTPS nodes. This is the type listed in the type constraint for isel. But since we list a type there, it doesn't get checked during isel matching. llvm-svn: 367775
* [SelectionDAG] Add node creation debug message to getMemIntrinsicNode.Craig Topper2019-08-041-1/+3
| | | | llvm-svn: 367771
* [Transforms] Do not drop !preserve.access.index metadataYonghong Song2019-08-032-3/+7
| | | | | | | | | | | | | | | Currently, when a GVN or CSE optimization happens, the llvm.preserve.access.index metadata is dropped. This caused a problem for BPF AbstructMemberOffset phase as it relies on the metadata (debuginfo types). This patch added proper hooks in lib/Transforms to preserve !preserve.access.index metadata. A test case is added to ensure metadata is preserved under CSE. Differential Revision: https://reviews.llvm.org/D65700 llvm-svn: 367769
* [DAGCombiner] Prevent the combine added in r367710 from creating illegal ↵Craig Topper2019-08-031-1/+1
| | | | | | | | | | | | types after type legalization. This is further fix for PR42880. Sanjay already disabled the X86 TLI hook for non-simple types, but we should really call isTypeLegal here if we're after type legalization. llvm-svn: 367768
* [x86] change free truncate hook to handle only simple types (PR42880)Sanjay Patel2019-08-031-0/+2
| | | | | | | | | | | | | This avoids the crash from: https://bugs.llvm.org/show_bug.cgi?id=42880 ...and I think it's a proper constraint for the TLI hook. But that example raises questions about what happens to get us into this situation (created i29 types) and what happens later (why does legalization die on those types), so I'm not sure if we will resolve the bug based on this change. llvm-svn: 367766
* [WebAssembly] Fix allocsize attribute in sjlj loweringKeno Fischer2019-08-031-1/+14
| | | | | | | | | | | | | Summary: The allocsize attribute refers to call parameters by index. Thus, when we add the extra parameter in sjlj lowering, we need to increment the referenced paramater in the allocsize attribute to avoid angering the Verifier. Reviewed By: aheejin Differential Revision: https://reviews.llvm.org/D65470 llvm-svn: 367765
* [JITLink] Add support for MachO/x86-64 UNSIGNED relocs with length=2.Lang Hames2019-08-031-2/+22
| | | | | | | | | MachO/x86-64 UNSIGNED relocs are almost always 64-bit (length=3), but UNSIGNED relocs of length=2 are allowed if the target resides in the low 32-bits. This patch adds support for such relocations in JITLink (previously they would have triggered an unsupported relocation error). llvm-svn: 367764
* [JITLink] Fix error message formatting.Lang Hames2019-08-031-1/+1
| | | | llvm-svn: 367763
* [Attributor][NFC] run clang-format on Attributor.cppStefan Stipanovic2019-08-031-4/+5
| | | | llvm-svn: 367757
* Speculative CompilationPraveen Velliengiri2019-08-035-6/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [ORC] Remove Speculator Variants for Different Program Representations [ORC] Block Freq Analysis Speculative Compilation with Naive Block Frequency Add Applications to OrcSpeculation ORC v2 with Block Freq Query & Example Deleted BenchMark Programs Signed-off-by: preejackie <praveenvelliengiri@gmail.com> ORCv2 comments resolved [ORCV2] NFC ORCv2 NFC [ORCv2] Speculative compilation - CFGWalkQuery ORCv2 Adapting IRSpeculationLayer to new locking scheme llvm-svn: 367756
* IR: print value numbers for unnamed function argumentsTim Northover2019-08-032-0/+18
| | | | | | | | | | For consistency with normal instructions and clarity when reading IR, it's best to print the %0, %1, ... names of function arguments in definitions. Also modifies the parser to accept IR in that form for obvious reasons. llvm-svn: 367755
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Sylvestre Ledru2019-08-032-2/+2
| | | | | | llvm::Register as started by r367614. NFC llvm-svn: 367754
* [Thumb] Fix invalid symbol redefinition due to duplicated jumptable (PR42760)Nikita Popov2019-08-031-1/+2
| | | | | | | | | | | | | | | Fix for https://bugs.llvm.org/show_bug.cgi?id=42760. A tBR_JTr instruction is duplicated by tail duplication, which results in the same jumptable with the same label being emitted twice. Fix this by marking tBR_JTr as not duplicable. The corresponding ARM/Thumb instructions are already marked as not duplicable. Additionally also mark tTBB_JT and tTBH_JT to be consistent with Thumb2, even though this shouldn't be strictly necessary. Differential Revision: https://reviews.llvm.org/D65606 llvm-svn: 367753
* Emit diagnostic if an inline asm constraint requires an immediateBill Wendling2019-08-039-28/+67
| | | | | | | | | | | | | | | | | | Summary: An inline asm call can result in an immediate after inlining. Therefore emit a diagnostic here if constraint requires an immediate but one isn't supplied. Reviewers: joerg, mgorny, efriedma, rsmith Reviewed By: joerg Subscribers: asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, MaskRay, jyknight, dylanmckay, javed.absar, fedor.sergeev, jrtc27, Jim, krytarowski, eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60942 llvm-svn: 367750
* [Attributor] Fix dereferenceable callsite argument initializationHideto Ueno2019-08-031-2/+4
| | | | llvm-svn: 367748
* Re-commit "[GlobalISel] Add legalization support for non-power-2 loads and ↵Amara Emerson2019-08-022-12/+100
| | | | | | | | | | stores"" This is an old commit that exposed a bug in the GISel importer, which caused non-truncating stores to be selected for truncating store patterns. Now that's been fixed in r367737 this can go back in. llvm-svn: 367739
* [ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use ↵Craig Topper2019-08-021-3/+32
| | | | | | | | | | scalar bit tests for the branches for expandload/compressstore. Same as what was done for gather/scatter/load/store in r367489. Expandload/compressstore were delayed due to lack of constant masking handling that has since been fixed. llvm-svn: 367738
* [X86] Use the pointer VT for the Scale node when lowering x86 gather/scatter ↵Craig Topper2019-08-021-4/+12
| | | | | | | | | | | intrinsics. This is consistent with the target independent intrinsic handling. Not sure this really matters since we just pull the constant out using getZExtValue later. llvm-svn: 367736
* [BPF] Handling type conversions correctly for CO-REYonghong Song2019-08-023-180/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With newly added debuginfo type metadata for preserve_array_access_index() intrinsic, this patch did the following two things: (1). checking validity before adding a new access index to the access chain. (2). calculating access byte offset in IR phase BPFAbstractMemberAccess instead of when BTF is emitted. For (1), the metadata provided by all preserve_*_access_index() intrinsics are used to check whether the to-be-added type is a proper struct/union member or array element. For (2), with all available metadata, calculating access byte offset becomes easier in BPFAbstractMemberAccess IR phase. This enables us to remove the unnecessary complexity in BTFDebug.cpp. New tests are added for . user explicit casting to array/structure/union . global variable (or its dereference) as the source of base . multi demensional arrays . array access given a base pointer . cases where we won't generate relocation if we cannot find type name. Differential Revision: https://reviews.llvm.org/D65618 llvm-svn: 367735
* Remove support for unsupported MSVC versionsJF Bastien2019-08-022-15/+1
| | | | | | | | | | | | | | Re-land r367727 with the #if fixed. Reviewers: rnk, lebedev.ri Subscribers: hiraditya, jkorous, dexonsmith, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65662 llvm-svn: 367734
* Revert Fix and test inter-procedural register allocation for ARMDouglas Yung2019-08-024-17/+2
| | | | | | | | This reverts r367669 (git commit f6b00c279a5587a25876752a6ecd8da0bed959dc) This was breaking a build bot http://lab.llvm.org:8011/builders/netbsd-amd64/builds/21233 llvm-svn: 367731
* Revert "Remove support for unsupported MSVC versions"JF Bastien2019-08-022-1/+13
| | | | | | Mismatched preprocessor, I'll fix in a follow-up. llvm-svn: 367728
* Remove support for unsupported MSVC versionsJF Bastien2019-08-022-13/+1
| | | | | | | | | | | | Reviewers: rnk, lebedev.ri Subscribers: hiraditya, jkorous, dexonsmith, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65662 llvm-svn: 367727
* [Attributor] Using liveness in other attributes.Stefan Stipanovic2019-08-021-30/+139
| | | | | | | | | | | | Modifying other AbstractAttributes to use Liveness AA and skip dead instructions. Reviewers: jdoerfert, uenoku Subscribers: hiraditya, llvm-commits Differential revision: https://reviews.llvm.org/D65243 llvm-svn: 367725
* [AArch64][GlobalISel] Eliminate redundant G_ZEXT when the source is ↵Amara Emerson2019-08-021-0/+17
| | | | | | | | | | | | implicitly zext-loaded. These cases can come up when the extending loads combiner doesn't combine a zext(load) to a zextload op, due to some other operation being in between, which then gets simplified at a later stage. Differential Revision: https://reviews.llvm.org/D65360 llvm-svn: 367723
* [TargetLowering] SimplifyMultipleUseDemandedBits - don't assume ↵Simon Pilgrim2019-08-021-1/+1
| | | | | | | | INSERT_VECTOR_ELT value type is simple. Noticed by inspection - this was copied from the X86 target equivalent where we can assume its legal/simple. llvm-svn: 367721
* Use MCRegister in MCRegisterInfo's interfacesDaniel Sanders2019-08-026-19/+23
| | | | | | | | | | | | | | | | | Summary: As part of this, define DenseMapInfo for MCRegister (and Register while I'm at it) Depends on D65599 Reviewers: arsenm Subscribers: MatzeB, qcolombet, jvesely, wdng, nhaehnle, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65605 llvm-svn: 367719
* [Statepoints] Fix overalignment of loads in no-realign-stack functionsPhilip Reames2019-08-021-8/+15
| | | | | | | | This really should have been part of 366765. For some reason, I forgot to handle the corresponding load side, and the readable test cases (using deopt vs statepoints) turned out to be overly reduced. Oops. As seen in the test change, the problem was that we were using a load with alignment expectations rather than the unaligned variant when the stack alignment was less than that prefered type alignment. llvm-svn: 367718
* hwasan: Remove unused field CurModuleUniqueId. NFCI.Peter Collingbourne2019-08-021-2/+0
| | | | llvm-svn: 367717
* [ORC] Remove a dead method.Lang Hames2019-08-021-7/+0
| | | | llvm-svn: 367716
* [ScalarizeMaskedMemIntrin] Add constant mask support to expandload and ↵Craig Topper2019-08-021-0/+34
| | | | | | | | | | compressstore scalarization This adds support for generating all the loads or stores for a constant mask into a single basic block with no conditionals. Differential Revision: https://reviews.llvm.org/D65613 llvm-svn: 367715
* [ORC] Turn on symbol-flags overrides for LLJIT on Windows by default.Lang Hames2019-08-021-2/+8
| | | | | | | | | | | | | libObject does not apply the Exported flag to symbols in COFF object files, which can lead to assertions when the symbol flags initially derived from IR added to the JIT clash with the flags seen by the JIT linker. Both RTDyldObjectLinkingLayer and ObjectLinkingLayer have a workaround for this: they can be told to override the flags seen by the linker with the flags attached to the materialization responsibility object that was passed down to the linker. This patch modifies LLJIT's setup code to enable this override by default on platforms where COFF is the default object format. llvm-svn: 367712
* [DAGCombiner] try to convert opposing shifts to castsSanjay Patel2019-08-021-0/+26
| | | | | | | | | | | | | | | | | | | | | This reverses a questionable IR canonicalization when a truncate is free: sra (add (shl X, N1C), AddC), N1C --> sext (add (trunc X to (width - N1C)), AddC') https://rise4fun.com/Alive/slRC More details in PR42644: https://bugs.llvm.org/show_bug.cgi?id=42644 I limited this to pre-legalization for code simplicity because that should be enough to reverse the IR patterns. I don't have any evidence (no regression test diffs) that we need to try this later. Differential Revision: https://reviews.llvm.org/D65607 llvm-svn: 367710
* Temporarily Revert "Changing representation of cv_def_range directives in ↵Eric Christopher2019-08-027-218/+34
| | | | | | | | | | Codeview debug info assembly format for better readability" This is breaking bots and the author asked me to revert. This reverts commit 367704. llvm-svn: 367707
* Changing representation of cv_def_range directives in Codeview debug info ↵Nilanjana Basu2019-08-027-34/+218
| | | | | | assembly format for better readability llvm-svn: 367704
* [AArch64][GlobalISel] Support the neg_addsub_shifted_imm32 patternJessica Paquette2019-08-022-12/+65
| | | | | | | | | | | Add an equivalent ComplexRendererFns function for SelectNegArithImmed. This allows us to select immediate adds of -1 by turning them into subtracts. Update select-binop.mir to show that the pattern works. Differential Revision: https://reviews.llvm.org/D65460 llvm-svn: 367700
* [SimplifyCFG] Cleanup redundant conditions [NFC].Alina Sbirlea2019-08-021-10/+8
| | | | | | | | | | | | | | | | | | Summary: Since the for loop iterates over BB's predecessors, the branch conditions found must have BB as one of the successors. For an unconditional branch the successor must be BB, added `assert`. For a conditional branch, one of the two successors must be BB, simplify `else if` to `else` and `assert`. Sink common instructions outside the if/else block. Reviewers: sanjoy.google Subscribers: jlebar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65596 llvm-svn: 367699
* Fix ARC after r367633Daniel Sanders2019-08-021-4/+2
| | | | llvm-svn: 367697
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