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* Add a description for AMD's bdver4 (aka Excavator).Benjamin Kramer2014-05-022-0/+9
| | | | | | This is just bdver3 + AVX2 + BMI2. llvm-svn: 207847
* R600/SI: Add processor type for Mullins.Tom Stellard2014-05-021-0/+2
| | | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> llvm-svn: 207846
* R600: Expand vector sin and cos.Tom Stellard2014-05-021-0/+2
| | | | | | | | v2: move code to AMDGPUISelLowering.cpp squash with tests (both EG and SI) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207845
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+2
| | | | llvm-svn: 207844
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-027-36/+231
| | | | | | | | | | | | | | | | | | The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 llvm-svn: 207843
* AArch64/ARM64: add patterns for post-indexed ST1 ops.Tim Northover2014-05-021-0/+47
| | | | llvm-svn: 207840
* ARM64: refactor NEON post-indexed loads & stores (MC).Tim Northover2014-05-023-987/+443
| | | | | | | | | | | | | | | | | | | Previously, LLVM had no knowledge that these instructions actually modified their address register: fine if they never end up in CodeGen, but when I'd rather like to write some patterns for them it becomes a disaster. The change is mostly straightforward, I think the most significant design decision was to *always* put the address write-back first. This allows loads and stores to be accessed more uniformly, for example permitting the continued sharing of the InstAlias definitions. I also discovered that the custom Decode logic is no longer needed, so I removed it. No tests, because there should be no functionality change. llvm-svn: 207839
* AArch64/ARM64: support indexed loads/stores on vector types.Tim Northover2014-05-024-1/+72
| | | | | | | | While post-indexed LD1/ST1 instructions do exist for vector loads, this patch makes use of the more flexible addressing-modes in LDR/STR instructions. llvm-svn: 207838
* Allow SelectionDAG::FoldConstantArithmetic to work when it's called with a ↵Benjamin Kramer2014-05-021-2/+8
| | | | | | vector VT but scalar values. llvm-svn: 207835
* Fold strlen(expr ? "str1" : "str2") to x ? len1 : len2. This fires about 330 ↵Nick Lewycky2014-05-021-0/+15
| | | | | | times in a bootstrap of clang. llvm-svn: 207828
* [Stackmaps] Pacify windows buildbot.Juergen Ributzka2014-05-011-0/+3
| | | | llvm-svn: 207807
* [Stackmaps] Add command line option to specify the stackmap version.Juergen Ributzka2014-05-011-1/+10
| | | | llvm-svn: 207805
* [Stackmaps] Refactor serialization code. No functional change intended.Juergen Ributzka2014-05-011-125/+144
| | | | llvm-svn: 207804
* [Stackmaps] Replace the custom ConstantPool class with a MapVector.Juergen Ributzka2014-05-011-5/+7
| | | | llvm-svn: 207803
* [IR] Make {extract,insert}element accept an index of any integer type.Michael J. Spencer2014-05-014-15/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given the following C code llvm currently generates suboptimal code for x86-64: __m128 bss4( const __m128 *ptr, size_t i, size_t j ) { float f = ptr[i][j]; return (__m128) { f, f, f, f }; } ================================================= define <4 x float> @_Z4bss4PKDv4_fmm(<4 x float>* nocapture readonly %ptr, i64 %i, i64 %j) #0 { %a1 = getelementptr inbounds <4 x float>* %ptr, i64 %i %a2 = load <4 x float>* %a1, align 16, !tbaa !1 %a3 = trunc i64 %j to i32 %a4 = extractelement <4 x float> %a2, i32 %a3 %a5 = insertelement <4 x float> undef, float %a4, i32 0 %a6 = insertelement <4 x float> %a5, float %a4, i32 1 %a7 = insertelement <4 x float> %a6, float %a4, i32 2 %a8 = insertelement <4 x float> %a7, float %a4, i32 3 ret <4 x float> %a8 } ================================================= shlq $4, %rsi addq %rdi, %rsi movslq %edx, %rax vbroadcastss (%rsi,%rax,4), %xmm0 retq ================================================= The movslq is uneeded, but is present because of the trunc to i32 and then sext back to i64 that the backend adds for vbroadcastss. We can't remove it because it changes the meaning. The IR that clang generates is already suboptimal. What clang really should emit is: %a4 = extractelement <4 x float> %a2, i64 %j This patch makes that legal. A separate patch will teach clang to do it. Differential Revision: http://reviews.llvm.org/D3519 llvm-svn: 207801
* Remove HexagonTargetMachine::addPassesForOptimizations; it is not needed any ↵Pranav Bhandarkar2014-05-012-16/+0
| | | | | | more. llvm-svn: 207800
* Add basic functionality for assignment of ints.Reed Kotler2014-05-011-1/+167
| | | | | | | | | | | | | | | This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel Test Plan: simplestore.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3527 llvm-svn: 207790
* Fix uninitialized variable introduced in r207739.David Blaikie2014-05-011-1/+1
| | | | | | | | | | This was initialized by llvm-mc (calling setDwarfVersion) but other clients (such as clang, llc, etc) aren't necessarily initializing this so we were getting garbage DWARF version values in the output. Initialize it to a reasonable default (the same default used in llvm-mc, though this is higher than it was (2) previously). llvm-svn: 207788
* Don't propagate StorageClass and ComplexType to aliases.Rafael Espindola2014-05-011-2/+1
| | | | | | | | | This matches gas' behaviour on COFF. I think that this yak is now sufficiently shaved for aliases with offset to work. llvm-svn: 207786
* Update and sort CMakeLists.Benjamin Kramer2014-05-011-5/+6
| | | | llvm-svn: 207785
* Add an optimization that does CSE in a group of similar GEPs.Eli Bendersky2014-05-013-4/+601
| | | | | | | | | | | | | | This optimization merges the common part of a group of GEPs, so we can compute each pointer address by adding a simple offset to the common part. The optimization is currently only enabled for the NVPTX backend, where it has a large payoff on some benchmarks. Review: http://reviews.llvm.org/D3462 Patch by Jingyue Wu. llvm-svn: 207783
* PR19623: Implement typedefs of void.David Blaikie2014-05-011-1/+0
| | | | | | | | This the LLVM portion that will allow Clang and other frontends to emit typedefs of void by providing a null type for the typedef's underlying type. llvm-svn: 207777
* Fixing a cast-qual warning. getBufferStart() and getBufferEnd() both return ↵Aaron Ballman2014-05-011-2/+3
| | | | | | | | a const char *, so casting to non-const was triggering a warning (even though the assignment and usage was always const anyway). No functional changes intended. llvm-svn: 207774
* R600/SI: Fix verifier error with pseudo store instructions.Matt Arsenault2014-05-011-1/+1
| | | | | | | | Use i32 instead of specifying SReg_32. When this is the pseudo INDIRECT_BASE_ADDR, this would give a bogus verifier error. llvm-svn: 207770
* Compute the correct section for zed = foo + 1 in COFF.Rafael Espindola2014-05-011-10/+9
| | | | | | | | | This fixes pr19147. There are a few more related issues to fix, but the testcase in the bug now passes. llvm-svn: 207763
* Move getBaseSymbol somewhere the COFF writer can use.Rafael Espindola2014-05-012-26/+25
| | | | | | I will use it there in a second. llvm-svn: 207761
* [ARM64] Prefer generation of bzero on Darwin onlyBradley Smith2014-05-011-2/+5
| | | | llvm-svn: 207760
* Make getBaseSymbol non recursive.Rafael Espindola2014-05-011-3/+5
| | | | llvm-svn: 207759
* Don't force symbols to be globals in .thumb_set.Rafael Espindola2014-05-011-5/+2
| | | | | | | | | | | | | | | | | | | | | | We currently force symbols to be globals in .thumb_set. The intent seems to be that given .thumb_set foo, bar we emit an undefined symbol to bar if it is never defined. The side effect is that we mark bar as global, even if it is defined, which gas does not. Producing an undefined reference to bar is a general difference from MC and gas. For example, given a = b gas will produce an undefined reference to b, MC will not. I would be surprised if any code depends on this, but it it does, we should fix the general difference, not special case .thumb_set. llvm-svn: 207757
* AArch64/ARM64: print BFM instructions as BFI or BFXILTim Northover2014-05-011-0/+27
| | | | | | | The canonical form of the BFM instruction is always one of the more explicit extract or insert operations, which makes reading output much easier. llvm-svn: 207752
* [LCG] Add the other simple edge insertion API to the call graph. ThisChandler Carruth2014-05-011-0/+15
| | | | | | | | | just connects an SCC to one of its descendants directly. Not much of an impact. The last one is the hard one -- connecting an SCC to one of its ancestors, and thereby forming a cycle such that we have to merge all the SCCs participating in the cycle. llvm-svn: 207751
* [LCG] Don't lookup the child SCC twice. Spotted this by inspection, andChandler Carruth2014-05-011-2/+2
| | | | | | no functionality changed. llvm-svn: 207750
* [LCG] Add some basic methods for querying the parent/child relationshipsChandler Carruth2014-05-011-0/+15
| | | | | | | | of SCCs in the SCC DAG. Exercise them in the big graph test case. These will be especially useful for establishing invariants in insertion logic. llvm-svn: 207749
* Correction to assert statemtent to allow 32-bit unsigned numbers with the ↵Richard Barton2014-05-011-2/+2
| | | | | | | | top bit set. This fixes an ARM assembler crash - regression test added. llvm-svn: 207747
* Revert r205965, which essentially reverts r205018 for the second time.Chandler Carruth2014-05-011-65/+30
| | | | | | | | | | | | | | | | =[ Turns out that this was the root cause of PR19621. We found a crasher only recently (likely due to improvements elsewhere in the SLP vectorizer) but the reduced test case failed all the way back to here. I've confirmed that reverting this patch both fixes the reduced test case in PR19621 and the actual source file that led to it, so it seems to really be rooted here. I've replied to the commit thread with discussion of my (feeble) attempts to debug this. Didn't make it very far, so reverting now that we have a good test case so that things can get back to healthy while the debugging carries on. llvm-svn: 207746
* [ARM64] Conditionalize CPU specific system registers on subtarget featuresBradley Smith2014-05-015-18/+74
| | | | llvm-svn: 207742
* [mips] Move expansion of .cpsetup to target streamer.Matheus Almeida2014-05-013-51/+80
| | | | | | | | | | | | | | | Summary: There are two functional changes: 1) The directive is not expanded for the ASM->ASM code path. 2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3482 llvm-svn: 207741
* [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, ↵Daniel Sanders2014-05-011-3/+1
| | | | | | | | | | and drotrv GAS doesn't actually accept these particular cases. The mnemonic without the trailing 'v' still supports two-operand aliases. llvm-svn: 207740
* Record the DWARF version in MCContextOliver Stannard2014-05-011-2/+2
| | | | | | | Record the DWARF version in MCContext, and use it when emitting the dwarf version into the debug info. llvm-svn: 207739
* ARM: fix memory leak, simplify WoA stack probingSaleem Abdulrasool2014-05-011-9/+3
| | | | | | | | | This fixes the memory leak introduced with the initial addition of support for WoA stack probing. Now that the pseudo-instruction expansion can handle an external symbol, use that to generate the load which simplifies the logic as well as avoids the memory leak. llvm-svn: 207737
* ARM: support expanding external symbols in 32-bit movesSaleem Abdulrasool2014-05-011-2/+14
| | | | | | | | This enhances the expansion of the mov32imm pseudo-instruction to support an external symbol reference. This is motivated by a simplification of the stack probe emission for Windows on ARM (and fixing a leak). llvm-svn: 207736
* Speculatively roll back r207724-r207726, which are code cleanup changes andRichard Smith2014-05-011-30/+25
| | | | | | appear to be breaking a bootstrapped build of compiler-rt. llvm-svn: 207732
* If necessary for indirect encodings, emit stubs.Joerg Sonnenberger2014-05-011-0/+22
| | | | llvm-svn: 207730
* Start fixing pr19147.Rafael Espindola2014-05-011-10/+13
| | | | | | | This makes the coff writer compute the correct symbol value for the test in pr19147. The section is still incorrect, that will be fixed in a followup patch. llvm-svn: 207728
* LexicalScopes: Use unique_ptr to manage ownership of abstract LexicalScopes.David Blaikie2014-04-301-8/+9
| | | | llvm-svn: 207726
* Forgotten reformatting.David Blaikie2014-04-301-5/+9
| | | | llvm-svn: 207725
* LexicalScopes: use unique_ptr to own LexicalScope objects.David Blaikie2014-04-301-16/+16
| | | | | | Ownership of abstract scopes coming soon. llvm-svn: 207724
* Add missing breaks.Joerg Sonnenberger2014-04-301-0/+3
| | | | llvm-svn: 207723
* Switch over getArch()'s result.Joerg Sonnenberger2014-04-301-15/+28
| | | | llvm-svn: 207721
* Use a single data structure to store all user variables in DwarfDebugAlexey Samsonov2014-04-303-19/+15
| | | | | | | | | | | | | | | | | | Summary: Get rid of UserVariables set, and turn DbgValues into MapVector to get a fixed ordering, as suggested in review for http://reviews.llvm.org/D3573. Test Plan: llvm regression tests Reviewers: dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3579 llvm-svn: 207720
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