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* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-01411-1883/+1883
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [LV] Preserve inbounds on created GEPsDaniel Neilson2018-05-011-3/+22
| | | | | | | | | | | | | | | | | | | Summary: This is a fix for PR23997. The loop vectorizer is not preserving the inbounds property of GEPs that it creates. This is inhibiting some optimizations. This patch preserves the inbounds property in the case where a load/store is being fed by an inbounds GEP. Reviewers: mkuper, javed.absar, hsaito Reviewed By: hsaito Subscribers: dcaballe, hsaito, llvm-commits Differential Revision: https://reviews.llvm.org/D46191 llvm-svn: 331269
* Fix the issue that ComputeValueKnownInPredecessors only handles the case whenWei Mi2018-05-011-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | phi is on lhs of a comparison op. For the following testcase, L1: %t0 = add i32 %m, 7 %t3 = icmp eq i32* %t2, null br i1 %t3, label %L3, label %L2 L2: %t4 = load i32, i32* %t2, align 4 br label %L3 L3: %t5 = phi i32 [ %t0, %L1 ], [ %t4, %L2 ] %t6 = icmp eq i32 %t0, %t5 br i1 %t6, label %L4, label %L5 We know if we go through the path L1 --> L3, %t6 should always be true. However currently, if the rhs of the eq comparison is phi, JumpThreading fails to evaluate %t6 to true. And we know that Instcombine cannot guarantee always canonicalizing phi to the left hand side of the comparison operation according to the operand priority comparison mechanism in instcombine. The patch handles the case when rhs of the comparison op is a phi. Differential Revision: https://reviews.llvm.org/D46275 llvm-svn: 331266
* [X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-0110-89/+22
| | | | | | Removes more WriteFShuffle InstRW overrides llvm-svn: 331264
* [X86] Convert all uses of WriteFShuffle to X86SchedWriteWidths.Simon Pilgrim2018-05-012-123/+153
| | | | | | In preparation of splitting WriteFShuffle by vector width. llvm-svn: 331262
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store ↵Sander de Smalen2018-05-012-1/+43
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46121 llvm-svn: 331260
* Reland r331175: "[mips] Fix the predicates of jump and branch and link ↵Simon Dardis2018-05-014-50/+69
| | | | | | | | | | | | | | | | instructions" The previous version of this patch restricted the 'jal' instruction to MIPS and microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal as an alias for balc. Original commit message: > Reviewers: smaksimovic, atanasyan, abeserminji > > Differential Revision: https://reviews.llvm.org/D46114 > llvm-svn: 331259
* [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-0110-38/+16
| | | | | | This removes all the WriteVecLogic InstRW overrides. llvm-svn: 331258
* [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed caseOmer Paparo Bivas2018-05-011-1/+12
| | | | | | | Differential Revision: https://reviews.llvm.org/D45731 Change-Id: I85d4226504e954933c41598327c91b2d08192a9d llvm-svn: 331257
* [X86] Convert all uses of WriteFLogic/WriteVecLogic to X86SchedWriteWidths.Simon Pilgrim2018-05-012-141/+157
| | | | | | In preparation of splitting WriteVecLogic by vector width. llvm-svn: 331256
* [MC] Add llvm_unreachable to toString to fix compile time warning.Florian Hahn2018-05-011-2/+1
| | | | | | | | | | | | | Without this change, GCC 7 raises the warning below: control reaches end of non-void function Reviewers: sbc100, andreadb Reviewed By: andreadb Differential Revision: https://reviews.llvm.org/D46304 llvm-svn: 331255
* [X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.Simon Pilgrim2018-05-016-39/+25
| | | | | | Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view. llvm-svn: 331253
* [X86] Correct spill slot size.Andrea Di Biagio2018-05-011-2/+2
| | | | | | | | | | | | | | | This patch fixes a bug introduced by revision 330778 (originally reviewed at: https://reviews.llvm.org/D44782), where function isFrameLoadOpcode returned the wrong number of bytes read for opcodes VMOVSSrm and VMOVSDrm. This corrects that mistake, and extends the regression test to catch cases where the dead stores should be removed. Patch by Jeremy Morse. Differential Revision: https://reviews.llvm.org/D46256 llvm-svn: 331252
* NFC, Avoid a warning in WasmObjectWriterGabor Buella2018-05-011-0/+2
| | | | | | | | | | The warning was (introduced in r331220): lib/MC/WasmObjectWriter.cpp:51:1: warning: control reaches end of non-void function [-Wreturn-type] } ^ llvm-svn: 331251
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-016-2/+57
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D45983 llvm-svn: 331248
* [PM/LoopUnswitch] Remove the last manual domtree update code from loopChandler Carruth2018-05-011-170/+18
| | | | | | | | | unswitch and replace it with the amazingly simple update API code. This addresses piles of FIXMEs around the update logic here and makes everything substantially simpler. llvm-svn: 331247
* [PM/LoopUnswitch] Add back a successor set that was removed based onChandler Carruth2018-05-011-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | code review. It turns out this *is* necessary, and I read the comment on the API correctly the first time. ;] The `applyUpdates` routine requires that updates are "balanced". This is in order to cleanly handle cycles like inserting, removing, nad then re-inserting the same edge. This precludes inserting the same edge multiple times in a row as handling that would cause the insertion logic to become *ordered* instead of *unordered* (which is what the API provides). It happens that in this specific case nothing (other than an assert and contract violation) goes wrong because we're never inserting and removing the same edge. The implementation *happens* to do the right thing to eliminate redundant insertions in that case. But the requirement is there and there is an assert to catch it. Somehow, after the code review I never did another asserts-clang build testing loop-unswich for a long time. As a consequence, I didn't notice this despite a bunch of testing going on, but it shows up immediately with an asserts build of clang itself. llvm-svn: 331246
* [X86] Remove 'opaque ptr' from the intel syntax parser and printer.Craig Topper2018-05-016-58/+55
| | | | | | | | Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing. We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does. llvm-svn: 331243
* Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug ↵Eric Christopher2018-05-0112-222/+280
| | | | | | | | | | | | | | | | | info emission." This appears to have some issues associated with the file directive output causing multiple global symbols with the name "file" to be emitted into a startup section. I'm investigating more specific causes and working with the original author. This reverts commit r330271. Also Revert "[DEBUGINFO, NVPTX] Add the test for the debug info of the local" This reverts commit r330592 and the follow up of 330779 as the testcase is dependent upon r330271. llvm-svn: 331237
* [ModRefInfo] Rename local variable IsMustAlias to avoid shadowing MustAlias ↵Alina Sbirlea2018-04-301-3/+3
| | | | | | enum entry. llvm-svn: 331222
* [SimplifyCFG] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).Florian Hahn2018-04-301-37/+14
| | | | | | | | | | | | | | This patch updates some code responsible the skip debug info to use BasicBlock::instructionsWithoutDebug. I think this makes things slightly simpler and more direct. Reviewers: aprantl, vsk, hans, danielcdh Reviewed By: hans Differential Revision: https://reviews.llvm.org/D46252 llvm-svn: 331221
* [WebAssembly] MC: Improve debug outputSam Clegg2018-04-301-8/+33
| | | | llvm-svn: 331220
* [LivePhysRegs] Remove registers clobbered by regmasks from the live setKrzysztof Parzyszek2018-04-302-6/+5
| | | | | | | | Dead defs were being removed from the live set (in stepForward), but registers clobbered by regmasks weren't (more specifically, they were actually removed by removeRegsInMask, but then they were added back in). llvm-svn: 331219
* [MC] Change AsmParser to leverage Assembler during evaluationNirav Dave2018-04-306-20/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | Teach AsmParser to check with Assembler for when evaluating constant expressions. This improves the handing of preprocessor expressions that must be resolved at parse time. This idiom can be found as assembling-time assertion checks in source-level assemblers. Note that this relies on the MCStreamer to keep sufficient tabs on Section / Fragment information which the MCAsmStreamer does not. As a result the textual output may fail where the equivalent object generation would pass. This can most easily be resolved by folding the MCAsmStreamer and MCObjectStreamer together which is planned for in a separate patch. Currently, this feature is only enabled for assembly input, keeping IR compilation consistent between assembly and object generation. Reviewers: echristo, rnk, probinson, espindola, peter.smith Reviewed By: peter.smith Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45164 llvm-svn: 331218
* [LoopSimplify] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).Florian Hahn2018-04-301-4/+1
| | | | | | | | | | | | | | This patch updates some code responsible the skip debug info to use BasicBlock::instructionsWithoutDebug. I think this makes things slightly simpler and more direct. Reviewers: aprantl, vsk, chandlerc Reviewed By: aprantl Differential Revision: https://reviews.llvm.org/D46253 llvm-svn: 331217
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-3019-90/+292
| | | | | | | | Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
* [MIR] Reset unique MBB numbering in MachineFunction::reset()Roman Tereshin2018-04-301-0/+1
| | | | | | | | | | | | | | No need to waste space nor number MBBs differently if MF gets recreated. Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar Reviewed By: qcolombet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46078 llvm-svn: 331213
* [DAGCombiner] rename function attribute for disabling ftrunc transformSanjay Patel2018-04-301-2/+2
| | | | | | | | | | This is the matching name change for the Clang patch at: D46236 rL331209 Differential Revision: https://reviews.llvm.org/D46237 llvm-svn: 331210
* [X86] Introduce X86SchedWriteWidths schedule wrapper for different vector ↵Simon Pilgrim2018-04-303-93/+160
| | | | | | | | | | | | | | widths. We need to split most of the scheduler classes by vector width to remove more of the InstRW overrides, this patch should make this easier/tidier by allowing us to pass the X86SchedWriteWidths wrapper to multi-width multiclasses and then split as required. I've included fields for Scl (scalar float/double), MMX (MMX integer), XMM, YMM and ZMM widths. These fields mostly share the same classes but it should give us the flexibility that we may need in the future. This patch has replaced a set of example SSE/AVX512 instruction cases but isn't exhaustive as it gets very noisy before we really need the functionality. Differential Revision: https://reviews.llvm.org/D46266 llvm-svn: 331208
* [InstCombine] Unfold masked merge with constant maskRoman Lebedev2018-04-301-1/+15
| | | | | | | | | | | | | | | | | Summary: As discussed in D45733, we want to do this in InstCombine. https://rise4fun.com/Alive/LGk Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: chandlerc, xbolva00, llvm-commits Differential Revision: https://reviews.llvm.org/D45867 llvm-svn: 331205
* [SystemZ] Handle SADDO et.al. and ADD/SUBCARRYUlrich Weigand2018-04-308-77/+614
| | | | | | | | | | | | | | | | This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO as well as ADDCARRY/SUBCARRY on top of the new CC implementation. In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead of the old ADDC/ADDE logic, which means we no longer need to use "glue" links for those instructions. This also allows making full use of the memory-based instructions like ALSI, which couldn't be recognized due to limitations in the DAG matcher previously. Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to directly using the ADD instructions and checking for a CC 3 result. llvm-svn: 331203
* [SystemZ] Do not use glue to represent condition code dependenciesUlrich Weigand2018-04-3011-242/+494
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, an instruction setting the condition code is linked to the instruction using the condition code via a "glue" link in the SelectionDAG. This has a number of drawbacks; in particular, it means the same CC cannot be used by multiple users. It also makes it more difficult to efficiently implement SADDO et. al. This patch changes the back-end to represent CC dependencies as normal values during SelectionDAG matching, along the lines of how this is handled in the X86 back-end already. In addition to the core mechanics of updating all relevant patterns, this requires a number of additional changes: - We now need to be able to spill/restore a CC value into a GPR if necessary. This means providing a copyPhysReg implementation for moves involving CC, and defining getCrossCopyRegClass. - Since we still prefer to avoid such spills, we provide an override for IsProfitableToFold to avoid creating a merged LOAD / ICMP if this would result in multiple users of the CC. - combineCCMask no longer requires a single CC user, and no longer need to be careful about preventing invalid glue/chain cycles. - emitSelect needs to be more careful in marking CC live-in to the basic block it generates. Also, we can now optimize the case of multiple subsequent selects with the same condition just like X86 does. llvm-svn: 331202
* Fix infinite loop after r331115Daniel Sanders2018-04-302-1/+6
| | | | | | | | There are two separate fixes here: * The lowering code for non-extending loads should report UnableToLegalize instead of emitting the same instruction. * The target should not be requesting lowering of non-extending loads. llvm-svn: 331201
* [DebugInfo] Prevent infinite recursion for malformed DWARFJonas Devlieghere2018-04-301-10/+30
| | | | | | | | | | | This prevents infinite recursion in DWARFDie::findRecursively for malformed DWARF where a DIE references itself. This fixes PR36257. Differential revision: https://reviews.llvm.org/D43092 llvm-svn: 331200
* [SLPVectorizer] Debug info shouldn't impact spill cost computation.Davide Italiano2018-04-301-1/+4
| | | | | | | | | | <rdar://problem/39794738> (Also, PR32761). Differential Revision: https://reviews.llvm.org/D46199 llvm-svn: 331199
* [X86][Atom] Remove unnecessary x87 load/move instrw overrides.Simon Pilgrim2018-04-301-3/+2
| | | | llvm-svn: 331198
* AMDGPU: Remove some dead codeTom Stellard2018-04-301-4/+0
| | | | llvm-svn: 331196
* [SystemZ] Refactor some VT casts in DAG match patternsUlrich Weigand2018-04-301-59/+59
| | | | | | | | | | | | | | In patterns where we need to specify a result VT, prefer [(set (tr.vt tr.op:$V1), (operator ...))] over [(set tr.op:$V1, (tr.vt (operator ...)))] This is NFC now, but simplifies some future changes. llvm-svn: 331192
* [SystemZ] Improve handling of Select pseudo-instructionsUlrich Weigand2018-04-306-26/+22
| | | | | | | | | | | | | | | If we have LOCR instructions, select them directly from SelectionDAG instead of first going through a pseudo instruction and then using the custom inserter to emit the LOCR. Provide Select pseudo-instructions for VR32/VR64 if we have vector instructions, to avoid having to go through the first 16 FPRs unnecessarily. If we do not have LOCFHR, prefer using LOCR followed by a move over a conditional branch. llvm-svn: 331191
* IWYU for llvm-config.h, removals. Also see r331184.Nico Weber2018-04-301-1/+0
| | | | llvm-svn: 331190
* [X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.Simon Pilgrim2018-04-301-1/+0
| | | | llvm-svn: 331188
* [X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.Simon Pilgrim2018-04-301-1/+1
| | | | llvm-svn: 331187
* AMDGPU/GlobalISel: Don't try to lower geometry shadersTom Stellard2018-04-301-0/+3
| | | | | | | | | | | | | | Summary: The AMDGPU_GS calling convention is not supported yet. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46041 llvm-svn: 331186
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-30127-14/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See r331124 for how I made a list of files missing the include. I then ran this Python script: for f in open('filelist.txt'): f = f.strip() fl = open(f).readlines() found = False for i in xrange(len(fl)): p = '#include "llvm/' if not fl[i].startswith(p): continue if fl[i][len(p):] > 'Config': fl.insert(i, '#include "llvm/Config/llvm-config.h"\n') found = True break if not found: print 'not found', f else: open(f, 'w').write(''.join(fl)) and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p` and tried to fix include ordering and whatnot. No intended behavior change. llvm-svn: 331184
* [BranchFolding] Salvage DBG_VALUE instructions from empty blocksBjorn Pettersson2018-04-301-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch will introduce copying of DBG_VALUE instructions from an otherwise empty basic block to predecessor/successor blocks in case the empty block is eliminated/bypassed. It is currently only done in one identified situation in the BranchFolding pass, before optimizing on empty block. It can be seen as a light variant of the propagation done by the LiveDebugValues pass, which unfortunately is executed after the BranchFolding pass. We only propagate (copy) DBG_VALUE instructions in a limited number of situations: a) If the empty BB is the only predecessor of a successor we can copy the DBG_VALUE instruction to the beginning of the successor (because the DBG_VALUE instruction is always part of the flow between the blocks). b) If the empty BB is the only successor of a predecessor we can copy the DBG_VALUE instruction to the end of the predecessor (because the DBG_VALUE instruction is always part of the flow between the blocks). In this case we add the DBG_VALUE just before the first terminator (assuming that the terminators do not impact the DBG_VALUE). A future solution, to handle more situations, could perhaps be to run the LiveDebugValues pass before branch folding? This fix is related to PR37234. It is expected to resolve the problem seen, when applied together with the fix in SelectionDAG from here: https://reviews.llvm.org/D46129 Reviewers: #debug-info, aprantl, rnk Reviewed By: #debug-info, aprantl Subscribers: ormris, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46184 llvm-svn: 331183
* [SelectionDAG] Improve selection of DBG_VALUE using a PHI node resultBjorn Pettersson2018-04-304-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When building the selection DAG at ISel all PHI nodes are selected and lowered to Machine Instruction PHI nodes before we start to create any SDNodes. So there are no SDNodes for values produced by the PHI nodes. In the past when selecting a dbg.value intrinsic that uses the value produced by a PHI node we have been handling such dbg.value intrinsics as "dangling debug info". I.e. we have not created a SDDbgValue node directly, because there is no existing SDNode for the PHI result, instead we deferred the creationg of a SDDbgValue until we found the first use of the PHI result. The old solution had a couple of flaws. The position of the selected DBG_VALUE instruction would end up quite late in a basic block, and for example not directly after the PHI node as in the LLVM IR input. And in case there were no use at all in the basic block the dbg.value could be dropped completely. This patch introduces a new VREG kind of SDDbgValue nodes. It is similar to a SDNODE kind of node, but it refers directly to a virtual register and not a SDNode. When we do selection for a dbg.value that is using the result of a PHI node we can do a lookup of the virtual register directly (as it already is determined for the PHI node) and create a SDDbgValue node immediately instead of delaying the selection until we find a use. This should fix a problem with losing debug info at ISel as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234). It does not resolve PR37234 completely, because the debug info is dropped later on in the BranchFolder (see D46184). Reviewers: #debug-info, aprantl Reviewed By: #debug-info, aprantl Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46129 llvm-svn: 331182
* NFC, Avoid a warning on pointer casting in PassPlugin.cppGabor Buella2018-04-301-2/+4
| | | | llvm-svn: 331179
* Revert "[mips] Fix the predicates of jump and branch and link instructions"Simon Dardis2018-04-303-67/+50
| | | | | | | | That commit broke one of the LLD builders, reverting while I investigate. This patch reverts r331175. llvm-svn: 331178
* [mips] Fix the predicates of jump and branch and link instructionsSimon Dardis2018-04-303-50/+67
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
* [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).Florian Hahn2018-04-301-8/+3
| | | | | | | | | | | | | | This patch updates some code responsible the skip debug info to use BasicBlock::instructionsWithoutDebug. I think this makes things slightly simpler and more direct. Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D46254 llvm-svn: 331174
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