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* [RegisterCoalescer] Ensure that both registers have subranges if one doesKrzysztof Parzyszek2018-08-151-1/+4
| | | | llvm-svn: 339792
* [RegisterCoalescer] Reset VNInfo def when copying segments overKrzysztof Parzyszek2018-08-151-2/+6
| | | | llvm-svn: 339788
* [WebAssembly] SIMD replace_laneDerek Schuff2018-08-151-1/+22
| | | | | | | | | | Implement and test replace_lane instructions. Patch by Thomas Lively Differential Revision: https://reviews.llvm.org/D50750 llvm-svn: 339786
* [RegAlloc] Check that subreg liveness tracking applies to given virtual regKrzysztof Parzyszek2018-08-151-1/+1
| | | | | | | | Subregister liveness applies selectively to register classes with certain properties. Make sure that when it's enabled, it applies to a given virtual register (in virtual register rewriter). llvm-svn: 339784
* [PowerPC] Enhance the selection(ISD::VSELECT) of vector typeNemanja Ivanovic2018-08-154-16/+9
| | | | | | | | | | | | | | | To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding. Use xxsel to match vselect if vsx is open, or use vsel. In order to do not write many patterns in td file, promote (for vector it's bitcast) all other type into v4i32 and only pattern match vselect of v4i32 into vsel or xxsel. Patch by wuzish Differential revision: https://reviews.llvm.org/D49531 llvm-svn: 339779
* [SystemZ] Replace subreg_r with subreg_hKrzysztof Parzyszek2018-08-155-24/+21
| | | | | | | | | | | | | | | | | | | | Change subreg_r32 -> subreg_h32 subreg_r64 -> subreg_h64 subreg_hr32 -> subreg_hh32 The subregisters subreg_r32 and subreg_r64 were added to emphasize the fact that modifying these subregisters may clobber the entire register. This is not necessarily the case for subreg_h32, et al. However, the ability to compose subreg_h64 with subreg_r32, and with subreg_h32 and subreg_l32 at the same time makes the compositions be treated as non-overlapping (leading to problems when tracking subreg liveness). See D50468 for more details. Differential Revision: https://reviews.llvm.org/D50725 llvm-svn: 339778
* [GVN] Fix typo in IsValueFullyAvailableInBlock. NFC.Marcello Maggioni2018-08-151-1/+1
| | | | | | | | DenseMap insert() method return a pair<iterator, bool> not pair<iterator, char> Noticed it and thought I might just fix it ... llvm-svn: 339777
* [SystemZ] New CL option to enable subreg livenessJonas Paulsson2018-08-152-0/+13
| | | | | | | | | | This option is needed to enable subreg liveness tracking during register allocation. Review: Ulrich Weigand https://reviews.llvm.org/D50779 llvm-svn: 339776
* [SimplifyCFG] Remove pointer from SmallPtrSet before deletionChijun Sima2018-08-151-3/+3
| | | | | | | | | | | | | | | | | Summary: Previously, `eraseFromParent()` calls `delete` which invalidates the value of the pointer. Copying the value of the pointer later is undefined behavior in C++11 and implementation-defined (which may cause a segfault on implementations having strict pointer safety) in C++14. This patch removes the BasicBlock pointer from related SmallPtrSet before `delete` invalidates it in the SimplifyCFG pass. Reviewers: kuhar, dmgreen, davide, trentxintong Reviewed By: kuhar, dmgreen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D50717 llvm-svn: 339773
* [ARM] TypeSize lower bound for ARMCodeGenPrepareSam Parker2018-08-151-1/+1
| | | | | | | | | We only try to promote types with are smaller than 16-bits, but we also need to check that the type is not less than 8-bits. Differential Revision: https://reviews.llvm.org/D50769 llvm-svn: 339770
* [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal typesNemanja Ivanovic2018-08-151-3/+10
| | | | | | | | | | | | | | When trying to combine a DAG that builds a vector out of sign-extensions of vector extracts, the code assumes legal input types. Due to that, we have to disable this combine prior to legalization. In some cases, the DAG will look slightly different after legalization so account for that in the matching code. This is a fix for https://bugs.llvm.org/show_bug.cgi?id=38087 Differential Revision: https://reviews.llvm.org/D49080 llvm-svn: 339769
* Remove lambda default argument to fix gcc pedantic warning.Simon Pilgrim2018-08-151-2/+2
| | | | llvm-svn: 339767
* [TargetLowering] Minor cleanup of TargetLowering::BuildSDIV. NFCI.Simon Pilgrim2018-08-151-21/+20
| | | | | | Pull out some types to match layout in TargetLowering::BuildUDIV. Early step towards adding non-uniform vector support. llvm-svn: 339763
* [UnJ] Rename hasInvariantIterationCount to ↵David Green2018-08-152-3/+3
| | | | | | | | hasIterationCountInvariantInParent NFC This hopefully describes the API of the function more precisely. llvm-svn: 339762
* [TargetLowering] Minor refactor to TargetLowering::BuildUDIV to merge ↵Simon Pilgrim2018-08-151-41/+31
| | | | | | | | scalar/vector magic value collection. NFCI. Use the same ISD::matchUnaryPredicate pattern that was used in D50392. llvm-svn: 339758
* [DagCombiner] Don't bother adding to the work list if TLI.BuildSDIVPow2 ↵Simon Pilgrim2018-08-151-4/+6
| | | | | | | | failed. NFCI. Matches the code in BuildSDIV/BuildUDIV llvm-svn: 339757
* [TargetLowering] Add support for non-uniform vectors to BuildExactSDIVSimon Pilgrim2018-08-151-12/+24
| | | | | | | | This patch refactors the existing BuildExactSDIV implementation to support non-uniform constant vector denominators. Differential Revision: https://reviews.llvm.org/D50392 llvm-svn: 339756
* [ARM] Allow signed icmps in ARMCodeGenPrepareSam Parker2018-08-151-22/+44
| | | | | | | | | | | Treat signed icmps as 'sinks', allowing them to be in the use-def tree, enabling more promotions to be performed. As a sink, any promoted incoming values need to be truncated before being used by the signed icmp. Differential Revision: https://reviews.llvm.org/D50067 llvm-svn: 339755
* [ARM] Allow pointer values in ARMCodeGenPrepareSam Parker2018-08-151-18/+30
| | | | | | | | | | | | Add pointers to the list of allowed types, but don't try to promote them. Also fixed a bug with the promotion of undef values, so a new value is now created instead of mutating in place. We also now only promote if there's an instruction in the use-def chains other than the icmp, sinks and sources. Differential Revision: https://reviews.llvm.org/D50054 llvm-svn: 339754
* [AliasSetTracker] Do not treat experimental_guard intrinsic as memory ↵Max Kazantsev2018-08-151-1/+7
| | | | | | | | | | | | | | | | writing instruction The `experimental_guard` intrinsic has memory write semantics to model the thread-exiting logic, but does not do any actual writes to memory. Currently, `AliasSetTracker` treats it as a normal memory write. As result, a loop-invariant load cannot be hoisted out of loop because the guard may possibly alias with it. This patch makes `AliasSetTracker` so that it doesn't treat guards as memory writes. Differential Revision: https://reviews.llvm.org/D50497 Reviewed By: reames llvm-svn: 339753
* [NFC] Refactoring of LoopSafetyInfo, step 1Max Kazantsev2018-08-155-25/+24
| | | | | | | | | Turn structure into class, encapsulate methods, add clarifying comments. Differential Revision: https://reviews.llvm.org/D50693 Reviewed By: reames llvm-svn: 339752
* [NFC] Add sanitizing assertion to ICF trackerMax Kazantsev2018-08-151-1/+3
| | | | llvm-svn: 339751
* [NFC][LICM] Make hoist method voidMax Kazantsev2018-08-151-4/+4
| | | | | | | | | Method hoist always returns true. This patch makes it void. Differential Revision: https://reviews.llvm.org/D50696 Reviewed By: hiraditya llvm-svn: 339750
* [X86] Change legacy SSE scalar fp to integer intrinsics to use specific ISD ↵Craig Topper2018-08-156-134/+112
| | | | | | | | | | | | opcodes instead of keeping as intrinsics. Unify SSE and AVX512 isel patterns. AVX512 added new versions of these intrinsics that take a rounding mode. If the rounding mode is 4 the new intrinsics are equivalent to the old intrinsics. The AVX512 intrinsics were being lowered to ISD opcodes, but the legacy SSE intrinsics were left as intrinsics. This resulted in the AVX512 instructions needing separate patterns for the ISD opcodes and the legacy SSE intrinsics. Now we convert SSE intrinsics and AVX512 intrinsics with rounding mode 4 to the same ISD opcode so we can share the isel patterns. llvm-svn: 339749
* [SDAG] Update the AVR backend for the SelectionDAG API changes inChandler Carruth2018-08-151-6/+2
| | | | | | r339740, fixing the build for this target. llvm-svn: 339748
* [hwasan] Add a basic API.Evgeniy Stepanov2018-08-151-5/+6
| | | | | | | | | | | | | | | | Summary: Add user tag manipulation functions: __hwasan_tag_memory __hwasan_tag_pointer __hwasan_print_shadow (very simple and ugly, for now) Reviewers: vitalybuka, kcc Subscribers: kubamracek, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D50746 llvm-svn: 339746
* [WebAssembly] SIMD SplatsDerek Schuff2018-08-151-0/+28
| | | | | | | | | | Implement and test SIMD splat ops. Patch by Thomas Lively Differential Revision: https://reviews.llvm.org/D50741 llvm-svn: 339744
* [SDAG] Remove the reliance on MI's allocation strategy forChandler Carruth2018-08-1421-202/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `MachineMemOperand` pointers attached to `MachineSDNodes` and instead have the `SelectionDAG` fully manage the memory for this array. Prior to this change, the memory management was deeply confusing here -- The way the MI was built relied on the `SelectionDAG` allocating memory for these arrays of pointers using the `MachineFunction`'s allocator so that the raw pointer to the array could be blindly copied into an eventual `MachineInstr`. This creates a hard coupling between how `MachineInstr`s allocate their array of `MachineMemOperand` pointers and how the `MachineSDNode` does. This change is motivated in large part by a change I am making to how `MachineFunction` allocates these pointers, but it seems like a layering improvement as well. This would run the risk of increasing allocations overall, but I've implemented an optimization that should avoid that by storing a single `MachineMemOperand` pointer directly instead of allocating anything. This is expected to be a net win because the vast majority of uses of these only need a single pointer. As a side-effect, this makes the API for updating a `MachineSDNode` and a `MachineInstr` reasonably different which seems nice to avoid unexpected coupling of these two layers. We can map between them, but we shouldn't be *surprised* at where that occurs. =] Differential Revision: https://reviews.llvm.org/D50680 llvm-svn: 339740
* [FPEnv] Scalarize StrictFP vector operationsCameron McInally2018-08-142-0/+50
| | | | | | | | Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
* [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.Eli Friedman2018-08-145-7/+31
| | | | | | | | | | | | | | | | | | | | | Intentionally excluding nodes from the DAGCombine worklist is likely to lead to weird optimizations and infinite loops, so it's generally a bad idea. To avoid the infinite loops, fix DAGCombine to use the isDesirableToCommuteWithShift target hook before performing the transforms in question, and implement the target hook in the ARM backend disable the transforms in question. Fixes https://bugs.llvm.org/show_bug.cgi?id=38530 . (I don't have a reduced testcase for that bug. But we should have sufficient test coverage for PerformSHLSimplify given that we're not playing weird tricks with the worklist. I can try to bugpoint it if necessary, though.) Differential Revision: https://reviews.llvm.org/D50667 llvm-svn: 339734
* [SanitizerCoverage] Add associated metadata to PC guards.Matt Morehouse2018-08-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Summary: Without this metadata LLD strips unused PC table entries but won't strip unused guards. This metadata also seems to influence the linker to change the ordering in the PC guard section to match that of the PC table section. The libFuzzer runtime library depends on the ordering of the PC table and PC guard sections being the same. This is not generally guaranteed, so we may need to redesign PC tables/guards/counters in the future. Reviewers: eugenis Reviewed By: eugenis Subscribers: kcc, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D50483 llvm-svn: 339733
* NFC: Clarify comment in loop vectorization legalityAnna Thomas2018-08-141-1/+2
| | | | | | | Clarifying the comment about PSCEV and external IV users by referencing the bug in question. llvm-svn: 339722
* [DebugInfoMetadata] Added DIFlags interface in DIBasicType.Adrian Prantl2018-08-149-15/+33
| | | | | | | | | | | Flags in DIBasicType will be used to pass attributes used in DW_TAG_base_type, such as DW_AT_endianity. Patch by Chirag Patel! Differential Revision: https://reviews.llvm.org/D49610 llvm-svn: 339714
* [WebAssembly] Fix encoding of non-SIMD vector-typed instructionsHeejin Ahn2018-08-142-29/+32
| | | | | | | | | | | | | | | | | | | Previously SIMD_I was the same as a normal instruction except for the addition of a HasSIM128 predicate. However, rL339186 changed the encoding of SIMD_I instructions to automatically contain the SIMD prefix byte. This broke the encoding of non-SIMD vector-typed instructions, which had instantiated SIMD_I. This CL corrects this error. Reviewers: aheejin Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D50682 Patch by Thomas Lively (tlively) llvm-svn: 339710
* [MS Demangler] Fix some minor formatting bugs.Zachary Turner2018-08-141-7/+5
| | | | | | | | | | | | | | | | 1) We print __restrict twice on member pointers. This is fixed and relevant tests are re-enabled. 2) Several tests were disabled because of printing slightly different output than undname. These were confirmed to be bugs in undname, so we just re-enable the tests. 3) The test for printing reference temporaries is re-enabled. This is a clang mangling extension, so we have some flexibility with how we demangle it. The output currently looks fine, so we just re-enable the test with no fixes. llvm-svn: 339708
* [WebAssembly] SIMD extract_laneHeejin Ahn2018-08-141-2/+62
| | | | | | | | | | | | | | | | | Implement instruction selection for all versions of the extract_lane instruction. Use explicit sext/zext to differentiate between extract_lane_s and extract_lane_u for applicable types, otherwise default to extract_lane_u. Reviewers: aheejin Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D50597 Patch by Thomas Lively (tlively) llvm-svn: 339707
* [Tablegen][MCInstPredicate] Removed redundant template argument from class ↵Andrea Di Biagio2018-08-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | TIIPredicate, and implemented verification rules for TIIPredicates. This patch removes redundant template argument `TargetName` from TIIPredicate. Tablegen can always infer the target name from the context. So we don't need to force users of TIIPredicate to always specify it. This allows us to better modularize the tablegen class hierarchy for the so-called "function predicates". class FunctionPredicateBase has been added; it is currently used as a building block for TIIPredicates. However, I plan to reuse that class to model other function predicate classes too (i.e. not just TIIPredicates). For example, this can be a first step towards implementing proper support for dependency breaking instructions in tablegen. This patch also adds a verification step on TIIPredicates in tablegen. We cannot have multiple TIIPredicates with the same name. Otherwise, this will cause build errors later on, when tablegen'd .inc files are included by cpp files and then compiled. Differential Revision: https://reviews.llvm.org/D50708 llvm-svn: 339706
* [LV] Teach about non header phis that have uses outside the loopAnna Thomas2018-08-142-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch teaches the loop vectorizer to vectorize loops with non header phis that have have outside uses. This is because the iteration dependence distance for these phis can be widened upto VF (similar to how we do for induction/reduction) if they do not have a cyclic dependence with header phis. When identifying reduction/induction/first order recurrence header phis, we already identify if there are any cyclic dependencies that prevents vectorization. The vectorizer is taught to extract the last element from the vectorized phi and update the scalar loop exit block phi to contain this extracted element from the vector loop. This patch can be extended to vectorize loops where instructions other than phis have outside uses. Reviewers: Ayal, mkuper, mssimpso, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D50579 llvm-svn: 339703
* Revert "[DebugInfo] Generate DWARF debug information for labels. (Fix leak ↵Bruno Cardoso Lopes2018-08-1416-407/+149
| | | | | | | | | | | | problems)" This reverts commit cb8c5e417d55141f3f079a8a876e786f44308336 / r339676. This causing a test to fail in http://green.lab.llvm.org/green/job/clang-stage1-configure-RA/48406/ LLVM :: DebugInfo/Generic/debug-label.ll llvm-svn: 339700
* [X86][SSE] Avoid duplicate shuffle input sources in ↵Simon Pilgrim2018-08-141-16/+19
| | | | | | | | | | combineX86ShufflesRecursively rL339686 added the case where a faux shuffle might have repeated shuffle inputs coming from either side of the OR(). This patch improves the insertion of the inputs into the source ops lists to account for this, as well as making it trivial to add support for shuffles with more than 2 inputs in the future. llvm-svn: 339696
* [DomTree] Cleanup Update and LegalizeUpdate API moved to Support header.Alina Sbirlea2018-08-141-1/+1
| | | | | | | | | | | | | | Summary: Clean-up following D50479. Make Update and LegalizeUpdate refer to the utilities in Support/CFGUpdate. Reviewers: kuhar Subscribers: sanjoy, jlebar, mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D50669 llvm-svn: 339694
* [DAG] Avoid redundant chain transversal in store merge cycle check. NFCI.Nirav Dave2018-08-141-1/+2
| | | | | | Patch by Henric Karlsson. llvm-svn: 339688
* [X86][SSE] Add shuffle combine support for OR(PSHUFB,PSHUFB) style patterns.Simon Pilgrim2018-08-141-0/+53
| | | | | | If each element is zero from one (or both) inputs then we can combine these into a single shuffle mask. llvm-svn: 339686
* [Inliner] add inliner stats to new pm version of inlinerFedor Sergeev2018-08-141-0/+3
| | | | | | Increment existing NumInlined and NumDeleted stats in InlinerPass::run. llvm-svn: 339682
* [X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to work with any ↵Simon Pilgrim2018-08-141-30/+31
| | | | | | | | vXi8 type. We still only use this for v16i8, but this cleans up the code to support v32i8/v64i8 sometime in the future. llvm-svn: 339679
* [DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)Hsiangkai Wang2018-08-1416-149/+407
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two forms for label debug information in DWARF format. 1. Labels in a non-inlined function: DW_TAG_label DW_AT_name DW_AT_decl_file DW_AT_decl_line DW_AT_low_pc 2. Labels in an inlined function: DW_TAG_label DW_AT_abstract_origin DW_AT_low_pc We will collect label information from DBG_LABEL. Before every DBG_LABEL, we will generate a temporary symbol to denote the location of the label. The symbol could be used to get DW_AT_low_pc afterwards. So, we create a mapping between 'inlined label' and DBG_LABEL MachineInstr in DebugHandlerBase. The DBG_LABEL in the mapping is used to query the symbol before it. The AbstractLabels in DwarfCompileUnit is used to process labels in inlined functions. We also keep a mapping between scope and labels in DwarfFile to help to generate correct tree structure of DIEs. It also generates label debug information under global isel. Differential Revision: https://reviews.llvm.org/D45556 llvm-svn: 339676
* [GlobalISel][IRTranslator] Fix a bug in handling repeating struct types ↵Amara Emerson2018-08-141-0/+2
| | | | | | | | during argument lowering. Differential Revision: https://reviews.llvm.org/D49442 llvm-svn: 339674
* Fix MSVC "compiler limit: blocks nested too deeply" error. NFCI.Simon Pilgrim2018-08-141-35/+19
| | | | | | MSVC only accepts if-else chains up to 127 blocks long. I've had to merge a number of intrinsic cases together to get back below this limit, resulting in some duplication of string matches; this shouldn't cause any notable increase in runtime (and even then only for old IR, nothing that clang currently emits). llvm-svn: 339666
* [X86] Constant folding of adds/subs intrinsicsTomasz Krupa2018-08-141-0/+98
| | | | | | | | | | | | | | Summary: This adds constant folding of signed add/sub with saturation intrinsics. Reviewers: craig.topper, spatel, RKSimon, chandlerc, efriedma Reviewed By: craig.topper Subscribers: rnk, llvm-commits Differential Revision: https://reviews.llvm.org/D50499 llvm-svn: 339659
* [RISCV] Fix incorrect use of MCInstBuilderRoger Ferrer Ibanez2018-08-141-8/+6
| | | | | | | | | | | | | | | | | | This is a fix for r339314. MCInstBuilder uses the named parameter idiom and an 'operator MCInst&' to ease the creation of MCInsts. As the object of MCInstBuilder owns the MCInst is manipulating, the lifetime of the MCInst is bound to that of MCInstBuilder. In r339314 I bound a reference to the MCInst in an initializer. The temporary of MCInstBuilder (and also its MCInst) is destroyed at the end of the declaration leading to a dangling reference. Fix this by using MCInstBuilder inside an argument of a function call. Temporaries in function calls are destroyed in the enclosing full expression, so the the reference to MCInst is still valid when emitToStreamer executes. llvm-svn: 339654
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