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* [RISCV][NFC] Replace hard-coded CSR duplication with symbolic referencesSam Elliott2019-07-054-39/+36
| | | | | | | | | | | | | | | | Reviewers: asb, lenary Reviewed By: asb, lenary Subscribers: MaskRay, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64139 Patch by James Clarke (jrtc27) llvm-svn: 365195
* [FileCheck] Fix comment in parseNumericVariableUseThomas Preud'homme2019-07-051-6/+6
| | | | | | | | | | | | | | | | | | | | Summary: Comment explaining the interaction between parsing of numeric variable definition and uses in parseNumericVariableUse is stale since it suggests both use and definition parsing is done in the same function. This was the case in a previous version of the patch committed as 71d3f227a790d6cf39d8c6267940e0dc0c237e11 but is no longer the case. This patch updates the comment accordingly. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya Tags: #llvm Differential Revision: https://reviews.llvm.org/D64227 llvm-svn: 365192
* [FileCheck] Factor some parsing checks outThomas Preud'homme2019-07-051-35/+14
| | | | | | | | | | | | | | | | | Summary: Both callers of parseNumericVariableDefinition() perform the same extra check that no character is found after the variable name. This patch factors out this check into parseNumericVariableDefinition(). Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya Tags: #llvm Differential Revision: https://reviews.llvm.org/D64226 llvm-svn: 365191
* [FileCheck] Add missing final dot in commentThomas Preud'homme2019-07-051-1/+1
| | | | llvm-svn: 365190
* [ThinLTO] Attempt to recommit r365040 after caching fixEugene Leviant2019-07-059-143/+307
| | | | | | | | | | | | | | It's possible that some function can load and store the same variable using the same constant expression: store %Derived* @foo, %Derived** bitcast (%Base** @bar to %Derived**) %42 = load %Derived*, %Derived** bitcast (%Base** @bar to %Derived**) The bitcast expression was mistakenly cached while processing loads, and never examined later when processing store. This caused @bar to be mistakenly treated as read-only variable. See load-store-caching.ll. llvm-svn: 365188
* Make joined instances of JoinedOrSeparate flags point to the unaliased args, ↵Nico Weber2019-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | like all other arg types do This fixes an 8-year-old regression. r105763 made it so that aliases always refer to the unaliased option – but it missed the "joined" branch of JoinedOrSeparate flags. (r162231 then made the Args classes non-virtual, and r169344 moved them from clang to llvm.) Back then, there was no JoinedOrSeparate flag that was an alias, so it wasn't observable. Now /U in CLCompatOptions is a JoinedOrSeparate alias in clang, and warn_slash_u_filename incorrectly used the aliased arg id (using the unaliased one isn't really a regression since that warning checks if the undefined macro contains slash or backslash and only then emits the warning – and no valid use will pass "-Ufoo/bar" or similar). Also, lld has many JoinedOrSeparate aliases, and due to this bug it had to explicitly call `getUnaliasedOption()` in a bunch of places, even though that shouldn't be necessary by design. After this fix in Option, these calls really don't have an effect any more, so remove them. No intended behavior change. (I accidentally fixed this bug while working on PR29106 but then wondered why the warn_slash_u_filename broke. When I figured it out, I thought it would make sense to land this in a separate commit.) Differential Revision: https://reviews.llvm.org/D64156 llvm-svn: 365186
* [Object/ELF.h] - Improve error reporting.George Rimar2019-07-051-2/+7
| | | | | | | | | | | | | | | | | The errors coming from ELF.h are usually not very useful because they are uninformative. This patch is a first step to improve the situation. I tested this patch with a run of check-llvm and found that few messages are untested. In this patch, I did not add more tests but marked all such cases with a "TODO" comment. For all tested messages I extended the error text to provide more details (see test cases changed). Differential revision: https://reviews.llvm.org/D64014 llvm-svn: 365183
* [X86][SSE] LowerINSERT_VECTOR_ELT - early out for out of range indicesSimon Pilgrim2019-07-051-3/+3
| | | | | | Fixes OSS-Fuzz #15662 llvm-svn: 365180
* [ARM] MVE VMOV immediate handlingDavid Green2019-07-055-30/+57
| | | | | | | | | | | | | This adds some handling for VMOVimm, using the same method that NEON uses. We create VMOVIMM/VMVNIMM/VMOVFPIMM nodes based on the immediate, and select them using the now renamed ARMvmovImm/etc. There is also an extra 64bit immediate mode that I have not yet added here. Code by David Sherwood Differential Revision: https://reviews.llvm.org/D63884 llvm-svn: 365178
* [ARM] MVE fp to int conversionsDavid Green2019-07-052-0/+26
| | | | | | | | This adds the patterns needed for fptosi and sitofp. Differential Revision: https://reviews.llvm.org/D63729 llvm-svn: 365176
* [RISCV] Delete a ctor that is commented out. NFCFangrui Song2019-07-051-2/+0
| | | | llvm-svn: 365175
* [X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate ↵Craig Topper2019-07-041-1/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | forms under optsize when the immediate has additional users. Summary: We attempt to prevent folding immediates with multiple users under optsize. But we only do this from store nodes and X86ISD::ADD/SUB/XOR/OR/AND patterns. We don't do it for ISD::ADD/SUB/XOR/OR/AND even though we count them as users when deciding whether to fold into other nodes. This leads to situations where we block folding to a compare for example, but still fold into an AND or OR as seen in PR27202. Unfortunately touching the isel patterns in tablegen for the ISD::ADD/SUB/XOR/OR/AND opcodes will cause the patterns to be unusable for fast isel. And we don't have a way to make a fast isel only pattern. To workaround this, this patch adds custom isel in front of the isel table that will select the non-immediate forms if the immediate has additional users. This may create some issues for ANDN and NOT matching. And there's room for improvement with unsigned 32 immediates on 64-bit AND. This patch needs more thorough test cases, but I wanted to get feedback on the direction. Please send me any other test cases you've seen in the wild. I think we probably have the same issue with the immediate matching when we fold RMW from X86ISD::ADD/SUB/XOR/OR/AND. And our TEST immedaite shrinking logic. Our cost modeling for immediates that can fit in a sign extended 8-bit immediate on a 16/32/64 bit operation is completely wrong. I also wonder if we should update the ConstantHoisting cost model and block folding for "opaque" constants. But of course constants can still be created by DAG combine and lowering optimizations. Fixes PR27202 Reviewers: spatel, RKSimon, andreadb Reviewed By: RKSimon Subscribers: jsji, hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59909 llvm-svn: 365163
* [mips] Refactor expandSeq and expandSeqI methods. NFCSimon Atanasyan2019-07-041-41/+43
| | | | llvm-svn: 365161
* [DAGCombiner] Don't combine (addcarry (uaddo X, Y), 0, Carry) -> (addcarry ↵Craig Topper2019-07-041-1/+4
| | | | | | | | | | | | | | | | | | | | | X, Y, Carry) if the Carry comes from the uaddo. Summary: The uaddo won't be removed and the addcarry will still be dependent on the uaddo. So we'll just increase the use count of X and Y and potentially require a COPY. Reviewers: spatel, RKSimon, deadalnix Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64190 llvm-svn: 365149
* [AMDGPU] Custom lower INSERT_SUBVECTOR v3, v4, v5, v8Tim Renouf2019-07-042-8/+37
| | | | | | | | | | | | | | | | | | | Summary: Since the changes to introduce vec3 and vec5, INSERT_VECTOR for these sizes has been marked "expand", which made LegalizeDAG lower it to loads and stores via a stack slot. The code got optimized a bit later, but the now-unused stack slot was never deleted. This commit avoids that problem by custom lowering INSERT_SUBVECTOR into an EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT for each element in the subvector to insert. V2: Addressed review comments re test. Differential Revision: https://reviews.llvm.org/D63160 Change-Id: I9e3c13e36f68cfa3431bb9814851cc1f673274e1 llvm-svn: 365148
* [InstCombine] allow undef elements when forming splat from chain of ↵Sanjay Patel2019-07-041-4/+17
| | | | | | | | | | | | | | | | | | insertelements We allow forming a splat (broadcast) shuffle, but we were conservatively limiting that to cases where all elements of the vector are specified. It should be safe from a codegen perspective to allow undefined lanes of the vector because the expansion of a splat shuffle would become the chain of inserts again. Forming splat shuffles can reduce IR and help enable further IR transforms. Motivating bugs: https://bugs.llvm.org/show_bug.cgi?id=42174 https://bugs.llvm.org/show_bug.cgi?id=16739 Differential Revision: https://reviews.llvm.org/D63848 llvm-svn: 365147
* Fix typos in comments and debug output.Jay Foad2019-07-041-3/+3
| | | | llvm-svn: 365146
* [AMDGPU] Correct the setting of `FlatScratchInit`.Michael Liao2019-07-041-1/+12
| | | | | | | | | | | | | | Summary: - That flag setting should skip spilling stack slot. Reviewers: arsenm, rampitec Subscribers: qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64143 llvm-svn: 365137
* Fix -Wdocumentation param warning.Simon Pilgrim2019-07-041-2/+2
| | | | | | Don't put the full stop at the end of a param name - it confuses the doxygen parser llvm-svn: 365128
* [X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> ↵Simon Pilgrim2019-07-041-8/+8
| | | | | | | | vpermilps(concat_vectors(x,y),c) Bitcast v4i32 to v8f32 and back again - it might be worth adding isel patterns for X86PShufd v8i32 on AVX1 targets like we did for X86Blendi to avoid the bitcasts? llvm-svn: 365125
* Fix MSVC "not all control paths return a value" warnings. NFCI.Simon Pilgrim2019-07-041-4/+2
| | | | llvm-svn: 365119
* [Remarks] Silence gcc warning by catching unhandled values in switchesMikael Holmen2019-07-041-0/+4
| | | | | | | | | | | | | | | | | | | Without this fix gcc (7.4) complains with ../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef)': ../lib/Remarks/RemarkParser.cpp:29:1: error: control reaches end of non-void function [-Werror=return-type] } ^ ../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef, const llvm::remarks::ParsedStringTable&)': ../lib/Remarks/RemarkParser.cpp:38:1: error: control reaches end of non-void function [-Werror=return-type] } ^ The Format enum currently only contains the value YAML which is indeed already handled in the switches, but gcc complains anyway. Adding a default case with an llvm_unreachable silences gcc. llvm-svn: 365118
* [ARM] Favour PL/MI over GE/LT when possibleDavid Green2019-07-041-0/+19
| | | | | | | | | | | | | | | The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
* [ARM] MVE bitwise instruction patternsDavid Green2019-07-042-1/+25
| | | | | | | | | | | | This adds patterns for the simpler VAND, VORR and VEOR bitwise vector instructions. It also adjusts the top16Zero PatLeaf to not match on vector instructions, which can otherwise cause problems. Code written by David Sherwood. Differential Revision: https://reviews.llvm.org/D63867 llvm-svn: 365113
* [NFC][PowerPC] Make the PowerPC scheduling strategy feature only control the ↵QingShan Zhang2019-07-041-10/+10
| | | | | | strategy instead of the scheduler. llvm-svn: 365110
* [X86] Use pointer sized indices instead of i32 for EXTRACT_VECTOR_ELT and ↵Craig Topper2019-07-041-2/+2
| | | | | | | | INSERT_VECTOR_ELT in a couple places. Most places already did this. llvm-svn: 365109
* [LoopPeel] Some small comment update. NFC.Serguei Katkov2019-07-041-3/+3
| | | | | | | Follow-up change of comment after https://reviews.llvm.org/D63917 is landed. llvm-svn: 365107
* [PowerPC] Support constraint code "ww"Fangrui Song2019-07-041-4/+6
| | | | | | | | | | | | | Summary: "ww" and "ws" are both constraint codes for VSX vector registers that hold scalar double data. "ww" is preferred for float while "ws" is preferred for double. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D64119 llvm-svn: 365106
* [PowerPC] Hardware Loop branch instruction's condition may not be icmp.Chen Zheng2019-07-041-1/+1
| | | | | | | This fixes pr42492. Differential Revision: https://reviews.llvm.org/D64124 llvm-svn: 365104
* [Remarks] Require an explicit format to the parserFrancis Visoiu Mistrih2019-07-043-11/+31
| | | | | | | | | Make the parser require an explicit format. This allows new formats to be easily added by following YAML as an example. llvm-svn: 365102
* [Remarks][NFC] Move the string table parsing out of the parser constructorFrancis Visoiu Mistrih2019-07-043-12/+11
| | | | | | Make the parser take an already-parsed string table. llvm-svn: 365101
* [WebAssembly] Update test failure explanationsDerek Schuff2019-07-041-2/+2
| | | | llvm-svn: 365100
* [MachO] Add valid architecture functionShoaib Meenai2019-07-041-19/+10
| | | | | | | | | | | Added array of valid architectures and function returning array. Modified llvm-lipo to include list of valid architectures in error message for invalid arch. Patch by Anusha Basana <anusha.basana@gmail.com> Differential Revision: https://reviews.llvm.org/D63735 llvm-svn: 365099
* [JITLink][ORC] Add EHFrameRegistrar interface, use in EHFrameRegistrationPlugin.Lang Hames2019-07-042-12/+25
| | | | | | | | Replaces direct calls to eh-frame registration with calls to methods on an EHFrameRegistrar instance. This allows clients to substitute a registrar that registers frames in a remote process via IPC/RPC. llvm-svn: 365098
* Revert [ThinLTO] Optimize writeonly globals outReid Kleckner2019-07-049-295/+143
| | | | | | | | | This reverts r365040 (git commit 5cacb914758c7f436b47c8362100f10cef14bbc4) Speculatively reverting, since this appears to have broken check-lld on Linux. Partial analysis in https://crbug.com/981168. llvm-svn: 365097
* [WebAssembly] Enable IndirectBrExpandPassDerek Schuff2019-07-033-9/+5
| | | | | | | | | | | | | Wasm doesn't have a direct way to lower indirectbr, so hook up the IndirectBrExpandPass to lower indirectbr into a switch. Fixes PR42498 Reviewers: aheejin Differential Revision: https://reviews.llvm.org/D64161 llvm-svn: 365096
* AMDGPU: Add pass to lower SGPR spillsMatt Arsenault2019-07-039-33/+346
| | | | | | | | | | | | | | | This is split out from my patches to split register allocation into a separate SGPR and VGPR phase, and has some parts that aren't yet used (like maintaining LiveIntervals). This simplifies making the frame pointer register callee saved. As it is now, the code to determine callee saves needs to predict all the possible SGPR spills and how many callee saved VGPRs are needed. By handling this before PrologEpilogInserter, it's possible to just check the spill objects that already exist. Change-Id: I29e6df4034afcf949e06f8ef44206acb94696f04 llvm-svn: 365095
* [JumpThreading] Fix threading with unusual PHI nodes.Eli Friedman2019-07-031-3/+16
| | | | | | | | | | | | | | | | | | | | If the block being cloned contains a PHI node, in general, we need to clone that PHI node, even though it's trivial. If the operand of the PHI is an instruction in the block being cloned, the correct value for the operand doesn't exist until SSAUpdater constructs it. We usually don't hit this issue because we try to avoid threading across loop headers, but it's possible to hit this in some cases involving irreducible CFGs. I added a flag to allow threading across loop headers to make the testcase easier to understand. Thanks to Brian Rzycki for reducing the testcase. Fixes https://bugs.llvm.org/show_bug.cgi?id=42085. Differential Revision: https://reviews.llvm.org/D63913 llvm-svn: 365094
* GlobalISel: Fix widenScalar for pointer typed G_MERGE_VALUESMatt Arsenault2019-07-031-1/+1
| | | | llvm-svn: 365093
* [Bitcode] Move Bitstream to a separate libraryFrancis Visoiu Mistrih2019-07-0312-7/+61
| | | | | | | | | | | | | | | | | | | | | | | | | This moves Bitcode/Bitstream*, Bitcode/BitCodes.h to Bitstream/. This is needed to avoid a circular dependency when using the bitstream code for parsing optimization remarks. Since Bitcode uses Core for the IR part: libLLVMRemarks -> Bitcode -> Core and Core uses libLLVMRemarks to generate remarks (see IR/RemarkStreamer.cpp): Core -> libLLVMRemarks we need to separate the Bitstream and Bitcode part. For clang-doc, it seems that it doesn't need the whole bitcode layer, so I updated the CMake to only use the bitstream part. Differential Revision: https://reviews.llvm.org/D63899 llvm-svn: 365091
* Revert "[AMDGPU] Kernel arg metadata: added support for "__hip_texture" type."Matt Arsenault2019-07-031-10/+0
| | | | | | | | This reverts commit r365073. This is crashing, and is improperly relying on IR type names. llvm-svn: 365087
* Teach ValueTracking that aarch64.irg result aliases its input.Evgeniy Stepanov2019-07-031-1/+2
| | | | | | | | | | | | Reviewers: javed.absar, olista01 Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64103 llvm-svn: 365079
* [LFTR] Use SCEVExpander for the pointer limit case instead of manual IR genPhilip Reames2019-07-031-10/+5
| | | | | | As noted in the test change, this is not trivially NFC, but all of the changes in output are cases where the SCEVExpander form is more canonical/optimal than the hand generation. llvm-svn: 365075
* [AMDGPU] Kernel arg metadata: added support for "__hip_texture" type.Konstantin Pyzhov2019-07-031-0/+10
| | | | | | | | | Summary: Hip texture type is equivalent to OpenCL image. So, we need to set the Image type for kernel arguments with __hip_texture type. Differential revision: https://reviews.llvm.org/D63850 llvm-svn: 365073
* [LFTR] Remove a stray variable shadow *of the same value* [NFC]Philip Reames2019-07-031-1/+0
| | | | llvm-svn: 365072
* [LFTR] Style and comment changes to clarify the narrow vs wide bitwidth ↵Philip Reames2019-07-031-17/+18
| | | | | | evaluation behavior [NFC] llvm-svn: 365071
* [LFTR] Sink the decision not use truncate scheme for constants into ↵Philip Reames2019-07-031-46/+43
| | | | | | | | genLoopLimit [NFC] We might as well just evaluate the constants using SCEV, and having the cases grouped makes the logic slightly easier to read anyway. llvm-svn: 365070
* Fix precedence in assert from r364961Jessica Paquette2019-07-031-1/+2
| | | | | | | | Precedence was wrong in an assert added in r364961. Add braces around the assertion condition to make it right. See: https://reviews.llvm.org/D64084 llvm-svn: 365069
* [LFTR] Remove falsely generalized (dead) code [NFC]Philip Reames2019-07-031-5/+2
| | | | llvm-svn: 365067
* [LFTR] Hoist extend expressions outside of loops w/o waiting for LICMPhilip Reames2019-07-031-1/+4
| | | | | | | | The motivation for this is two fold: 1) Make the output (and thus tests) a bit more readable to a human trying to understand the result of the transform 2) Reduce spurious diffs in a potential future change to restructure all of this logic to use SCEVExpander (which hoists by default) llvm-svn: 365066
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