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* SDAG: Update ChainNodesMatched during UpdateChains if a node is replacedJustin Bogner2017-01-301-1/+11
| | | | | | | | | | | Previously, we would hit UB (or the ISD::DELETED_NODE assert) if we happened to replace a node during UpdateChains, because it would be left in the list we were iterating over. This nulls out the pointer when that happens so that we can avoid the issue. Fixes llvm.org/PR31710 llvm-svn: 293522
* Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where ↵Simon Pilgrim2017-01-301-7/+3
| | | | | | possible. NFCI. llvm-svn: 293520
* [libFuzzer] Implement TmpDir() for Windows.Marcos Pividori2017-01-301-1/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D28977 llvm-svn: 293516
* NewGVN: Instead of changeToUnreachable, insert an instruction SimplifyCFG ↵Daniel Berlin2017-01-301-4/+5
| | | | | | will turn into unreachable when it runs llvm-svn: 293515
* AMDGPU: Make i32 uaddo/usubo legalMatt Arsenault2017-01-302-0/+20
| | | | llvm-svn: 293514
* DAG: Fold fneg into compare with constant into the constantMatt Arsenault2017-01-301-0/+10
| | | | | | | | fcmp (fneg x), c, pred -> fcmp x, -c, (swap pred) InstCombine already does this. llvm-svn: 293512
* [RDF] Extract the physical register information into a separate classKrzysztof Parzyszek2017-01-307-254/+344
| | | | llvm-svn: 293510
* Revert "AMDGPU/GlobalISel: Add support for simple shaders"Tom Stellard2017-01-3016-1140/+10
| | | | | | | | This reverts commit r293503. Revert while I investigate some of the buildbot failures. llvm-svn: 293509
* [InstCombine] use auto with obvious type; NFCSanjay Patel2017-01-301-3/+3
| | | | llvm-svn: 293508
* [InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2) for vectors ↵Sanjay Patel2017-01-301-20/+16
| | | | | | with splat constants llvm-svn: 293507
* unique_ptrify some containers in GlobalISel::RegisterBankInfoDavid Blaikie2017-01-301-19/+9
| | | | | | | | | To simplify/clarify memory ownership, make leaks (as one was found/fixed recently) harder to write, etc. (also, while I was there - removed a duplicate lookup in a container) llvm-svn: 293506
* AMDGPU: Fix atomic_inc/atomic_dec + ds_swizzle not being divergentMatt Arsenault2017-01-301-0/+3
| | | | llvm-svn: 293504
* AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-3016-10/+1140
| | | | | | | | | | | | Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293503
* Revert "NewGVN: Make unreachable blocks be marked with unreachable"Daniel Berlin2017-01-301-13/+18
| | | | | | | | | This reverts commit r293196 Besides making things look nicer, ATM, we'd like to preserve analysis more than we'd like to destroy the CFG. We'll probably revisit in the future llvm-svn: 293501
* [X86][SSE] Add support for combining PINSRW+ASSERTZEXT+PEXTRW patterns with ↵Simon Pilgrim2017-01-301-0/+20
| | | | | | target shuffles llvm-svn: 293500
* DAG: Constant fold fp16_to_fp/fp16_to_fpMatt Arsenault2017-01-301-0/+19
| | | | | | | This fixes emitting conversions of constants on targets without legal f16 that need to use these for legalization. llvm-svn: 293499
* [InstCombine] fixed to propagate 'exact' on lshrSanjay Patel2017-01-301-1/+1
| | | | | | | | | | | | | | | | | The original shift is bigger, so this may qualify as 'obvious', but here's an attempt at an Alive-based proof: Name: exact Pre: (C1 u< C2) %a = shl i8 %x, C1 %b = lshr exact i8 %a, C2 => %c = lshr exact i8 %x, C2 - C1 %b = and i8 %c, ((1 << width(C1)) - 1) u>> C2 Optimization is correct! llvm-svn: 293498
* [Coroutines] Add header guard to header that's missing one.Benjamin Kramer2017-01-301-0/+5
| | | | llvm-svn: 293494
* [Inliner] Fold analysis remarks into missed remarksAdam Nemet2017-01-301-15/+12
| | | | | | This significantly reduces the noise level of these messages. llvm-svn: 293492
* [RDF] Add phis for entry block live-ins (in addition to function live-ins)Krzysztof Parzyszek2017-01-303-14/+22
| | | | llvm-svn: 293491
* [Inliner] Fix a comment to match the code. NFC.Haicheng Wu2017-01-301-2/+2
| | | | | | | | TotalAltCost => TotalSecondaryCost Differential Revision: https://reviews.llvm.org/D29231 llvm-svn: 293490
* [InstCombine] enable lshr(shl X, C1), C2 folds for vectors with splat constantsSanjay Patel2017-01-301-25/+25
| | | | llvm-svn: 293489
* Only print architecture dependent flags for that architecture.Rafael Espindola2017-01-305-11/+18
| | | | | | | | | | Different architectures can have different meaning for flags in the SHF_MASKPROC mask, so we should always check what the architecture use before checking the flag. NFC for now, but will allow fixing the value of an xmos flag. llvm-svn: 293484
* [Hexagon] Make header self-contained.Benjamin Kramer2017-01-301-0/+3
| | | | llvm-svn: 293482
* [X86][MCU] Minor bug fix for r293469 + test caseAsaf Badouh2017-01-301-1/+1
| | | | llvm-svn: 293478
* AMDGPU: Remove a useless VI SMRD patternMarek Olsak2017-01-302-10/+0
| | | | | | | | | | | | Summary: already covered by complex patterns Reviewers: arsenm, nhaehnle, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28995 llvm-svn: 293477
* AMDGPU: Fix assembler encoding for EXP instructions on VIMarek Olsak2017-01-301-0/+2
| | | | | | | | | | Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28992 llvm-svn: 293476
* Revert "[MemorySSA] Revert r293361 and r293363, as the tests fail under asan."Daniel Berlin2017-01-302-15/+34
| | | | | | | This reverts commit r293471, reapplying r293361 and r293363 with a fix for an out-of-bounds read. llvm-svn: 293474
* [MemorySSA] Revert r293361 and r293363, as the tests fail under asan.Sam McCall2017-01-302-27/+12
| | | | llvm-svn: 293471
* [GlobalISel] Add support for indirectbrKristof Beyls2017-01-304-0/+25
| | | | | | Differential Revision: https://reviews.llvm.org/D28079 llvm-svn: 293470
* [X86][MCU] replace select with bit manipulation instead of branchesAsaf Badouh2017-01-301-2/+41
| | | | | | | | | Differential Revision: https://reviews.llvm.org/D28354 llvm-svn: 293469
* [AVX-512] Remove duplicate CodeGenOnly patterns for scalar register ↵Craig Topper2017-01-303-34/+14
| | | | | | | | broadcast. We can use COPY_TO_REGCLASS like AVX does. This causes stack spill slots be oversized sometimes, but the same should already be happening with AVX. llvm-svn: 293464
* Include LLVMDumpValue in release builds.Sam McCall2017-01-301-3/+1
| | | | | | This part of the C API is still used in language bindings. llvm-svn: 293460
* [LoopVectorize] Improve getVectorCallCost() getScalarizationOverhead() call.Jonas Paulsson2017-01-301-19/+8
| | | | | | | | | | | | | | By calling getScalarizationOverhead with the CallInst instead of the types of its arguments, we make sure that only unique call arguments are added to the scalarization cost. getScalarizationOverhead() is extended to handle calls by only passing on the actual call arguments (which is not all the operands). This also eliminates a wrapper function with the same name. review: Hal Finkel llvm-svn: 293459
* [AVX-512] Remove KSET0B/KSET1B in favor of the patterns that select ↵Craig Topper2017-01-302-3/+0
| | | | | | KSET0W/KSET1W for v8i1. llvm-svn: 293458
* [MemorySSA] Correct an assertion surrounding with parentheses.Davide Italiano2017-01-301-3/+2
| | | | llvm-svn: 293453
* [AVX-512] Don't reuse VSHLI/VSRLI for mask register shifts. VSHLI/VSHRI ↵Craig Topper2017-01-304-25/+37
| | | | | | shift within elements while KSHIFT moves whole elements. llvm-svn: 293448
* [X86][Disassembler] Added SALC instructionChris Ray2017-01-291-112/+118
| | | | | | | | | | | | Reviewers: joe.abbey, craig.topper Reviewed By: craig.topper Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D29201 llvm-svn: 293447
* [AVX-512] Fix lowering for mask register concatenation with undef in the ↵Craig Topper2017-01-291-1/+1
| | | | | | | | lower half. Previously this test case fired an assertion in getNode because we tried to create an insert_subvector with both input types the same size and the index pointing to half the vector width. llvm-svn: 293446
* [X86] Fixing flag usage for RCL and RCRChris Ray2017-01-291-970/+967
| | | | | | | | | | | | | | Summary: The RCL and RCR instructions use the carry flag. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29237 llvm-svn: 293441
* MachineInstr: Remove parameter from dump()Matthias Braun2017-01-292-3/+5
| | | | | | | | | | | | | The primary use of the dump() functions in LLVM is for use in a debugger. Unfortunately lldb does not seem to handle default arguments so using `p SomeMI.dump()` fails and you have to type the longer `p SomeMI.dump(nullptr)`. Remove the paramter to make the most common use easy. (You can always construct something like `p SomeMI.print(dbgs(),MyTII)` if you need more features). Differential Revision: https://reviews.llvm.org/D29241 llvm-svn: 293440
* [X86][SSE] Lower scalar_to_vector(0) to zero vectorSimon Pilgrim2017-01-291-4/+15
| | | | | | | | | | Replaces an xor+movd/movq with an xorps which will be shorter in codesize, avoid an int-fpu transfer, allow modern cores to fast path the result during decode and helps other combines recognise an all-zero vector. The only reason I can think of that we'd want to keep scalar_to_vector in this case is to help recognise the upper elts are undef but this doesn't seem to be a problem. Differential Revision: https://reviews.llvm.org/D29097 llvm-svn: 293438
* llvm-c: Keep LLVMDumpModule() even in release buildsMatthias Braun2017-01-291-4/+3
| | | | | | | | While this probably should be considered a dump debugger utility, the C API currently has no other ways to print a module to stderr for error reporting purposes, so keep it even in release builds. llvm-svn: 293436
* [InstCombine] enable (X >>?,exact C1) << C2 --> X << (C2 - C1) for vectors ↵Sanjay Patel2017-01-291-17/+17
| | | | | | with splats llvm-svn: 293435
* ARM: support `-mlong-calls` with AEABI TLS on ELFSaleem Abdulrasool2017-01-291-7/+28
| | | | | | | | | | Support lowering AEABI TLS access (__aeabi_read_tp) with long calls. This requires adjusting the call sequence to use an indirect call to get full addressability. Resolves PR31769! llvm-svn: 293433
* [ValueTracking] clean up lookThroughCast; NFCISanjay Patel2017-01-291-42/+48
| | | | | | | | | 1. Use auto with dyn_cast. 2. Don't use else after return. 3. Convert chain of 'else if' to switch. 4. Improve variable names. llvm-svn: 293432
* [X86 Codegen] Fixed a bug in unsigned saturationElena Demikhovsky2017-01-291-23/+1
| | | | | | | | | | | PACKUSWB converts Signed word to Unsigned byte, (the same about DW) and it can't be used for umin+truncate pattern. AVX-512 VPMOVUS* instructions fit the pattern since they convert Unsigned to Unsigned. See https://llvm.org/bugs/show_bug.cgi?id=31773 Differential Revision: https://reviews.llvm.org/D29196 llvm-svn: 293431
* NewGVN: Fix where newline is printed in debug printing of memory equivalenceDaniel Berlin2017-01-291-1/+1
| | | | llvm-svn: 293428
* [X86][GlobalISel] Add limited argument lowering support to the IRTranslator.Igor Breger2017-01-291-2/+71
| | | | | | | | | | | | | | | | Summary: Add limited (i8/i16/i32/i64) argument lowering support to the IRTranslator. Inspired by commit 289940. Reviewers: t.p.northover, qcolombet, ab, zvi, rovka Reviewed By: rovka Subscribers: dberris, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D28987 llvm-svn: 293427
* [ArgPromote] Move static helpers to modern LLVM naming conventions whileChandler Carruth2017-01-291-15/+15
| | | | | | | | | | here. NFC. Simple refactoring while prepping a port to the new PM. Differential Revision: https://reviews.llvm.org/D29249 llvm-svn: 293426
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