summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [codeview] Truncate records to maximum record size near 64KBReid Kleckner2016-10-052-4/+14
| | | | | | | | | | | | If we don't truncate, LLVM asserts when the label difference doesn't fit in a 16 bit field. This patch truncates two kinds of data: trailing null terminated names in symbol records, and inline line tables. The inline line table test that I have is too large (many MB), so I'm not checking it in. Hopefully fixes PR28264. llvm-svn: 283403
* Verifier: Reject any unknown named MD nodes in the llvm.dbg namespace.Adrian Prantl2016-10-051-2/+7
| | | | | | | | | | | | | This came out of a discussion in https://reviews.llvm.org/D25285. There used to be various other llvm.dbg.* nodes, but we don't support upgrading them and we want to reserve the namespace for future uses. This also removes an entirely obsolete and bitrotted testcase for PR7662. Reapplies 283390 with a forgotten testcase. llvm-svn: 283400
* Revert "Verifier: Reject any unknown named MD nodes in the llvm.dbg namespace."Adrian Prantl2016-10-051-7/+2
| | | | | | Forgot to add a testcase in r283390. llvm-svn: 283399
* Modify df_iterator to support post-order actionsDavid Callahan2016-10-057-9/+9
| | | | | | | | | | | | Summary: This makes a change to the state used to maintain visited information for depth first iterator. We know assume a method "completed(...)" which is called after all children of a node have been visited. In all existing cases, this method does nothing so this patch has no functional changes. It will however allow a client to distinguish back from cross edges in a DFS tree. Reviewers: nadav, mehdi_amini, dberlin Subscribers: MatzeB, mzolotukhin, twoh, freik, llvm-commits Differential Revision: https://reviews.llvm.org/D25191 llvm-svn: 283391
* Verifier: Reject any unknown named MD nodes in the llvm.dbg namespace.Adrian Prantl2016-10-051-2/+7
| | | | | | | | | | | This came out of a discussion in https://reviews.llvm.org/D25285. There used to be various other llvm.dbg.* nodes, but we don't support upgrading them and we want to reserve the namespace for future uses. This also removes an entirely obsolete and bitrotted testcase for PR7662. llvm-svn: 283390
* [WebAssembly] Add binary-encoding opcode values to instruction descriptions.Dan Gohman2016-10-058-133/+147
| | | | llvm-svn: 283389
* [codeview] Translate bitpiece metadata to DEFRANGE_SUBFIELD* recordsReid Kleckner2016-10-052-41/+76
| | | | | | | | | | | | | This allows LLVM to describe locations of aggregate variables that have been split by SROA. Fixes PR29141 Reviewers: amccarth, majnemer Differential Revision: https://reviews.llvm.org/D25253 llvm-svn: 283388
* [Object] Fix a crash in Archive::child_iterator's default constructor.Lang Hames2016-10-051-4/+7
| | | | | | | | | | To be default constructible, Archive::child_iterator needs to be able to construct an Archive::Child with a null parent, however Archive::Child's constructor always dereferenced its Parent argument to compute the remaining archive size. This commit fixes Archive::Child's constructor to only do the size calculation when the parent is non-null. llvm-svn: 283387
* [ARM] Use __rt_div functions for divrem on WindowsMartin Storsjo2016-10-051-21/+45
| | | | | | | | | | | | | | | | | | | | This avoids falling back to calling out to the GCC rem functions (__moddi3, __umoddi3) when targeting Windows. The __rt_div functions have flipped the two arguments compared to the __aeabi_divmod functions. To match MSVC, we emit a check for division by zero before actually calling the library function (even if the library function itself also might do the same check). Not all calls to __rt_div functions for division are currently merged with calls to the same function with the same parameters for the remainder. This is more wasteful than a div + mls as before, but avoids calls to __moddi3. Differential Revision: https://reviews.llvm.org/D24076 llvm-svn: 283383
* [Sparc] Implement UMUL_LOHI and SMUL_LOHI instead of MULHS/MULHU/MUL.James Y Knight2016-10-053-18/+6
| | | | | | | This is what the instruction-set actually provides, and the default expansions of the others into the lohi opcodes are good. llvm-svn: 283381
* [asan] Reapply: Switch to using dynamic shadow offset on iOSAnna Zaks2016-10-051-2/+3
| | | | | | | | | | The VM layout is not stable between iOS version releases, so switch to dynamic shadow offset. This is the LLVM counterpart of https://reviews.llvm.org/D25218 Differential Revision: https://reviews.llvm.org/D25219 llvm-svn: 283376
* [LV] Pass profitability analysis in vectorizer constructor (NFC)Matthew Simpson2016-10-051-23/+28
| | | | | | | | | The vectorizer already holds a pointer to one cost model artifact in a member variable (i.e., MinBWs). As we add more, it will be easier to communicate these artifacts to the vectorizer if we simply pass a pointer to the cost model instead. llvm-svn: 283373
* [RDF] Fix live def propagation through basic blockKrzysztof Parzyszek2016-10-051-45/+60
| | | | llvm-svn: 283371
* AMDGPU: Do not re-use tmpreg in spill/restore loweringMatthias Braun2016-10-051-2/+2
| | | | | | | | | The register scavenging code does not support multiple definitions of the same vreg. Differential Revision: https://reviews.llvm.org/D25220 llvm-svn: 283369
* [LV] Pass legality analysis in vectorizer constructor (NFC)Matthew Simpson2016-10-051-12/+12
| | | | | | | The vectorizer already holds a pointer to the legality analysis in a member variable, so it makes sense that we would pass it in the constructor. llvm-svn: 283368
* FastISel: Remove unused/un-overridden entry points. NFCI.Peter Collingbourne2016-10-051-23/+0
| | | | llvm-svn: 283366
* [LV] Remove obsolete comment (NFC)Matthew Simpson2016-10-051-3/+1
| | | | llvm-svn: 283365
* [LV] Use getScalarizationOverhead in memory instruction costs (NFC)Matthew Simpson2016-10-051-14/+10
| | | | | | | | | This patch refactors the cost estimation of scalarized loads and stores to reuse getScalarizationOverhead for the cost of the extractelement and insertelement instructions we might create. The existing code accounted for this cost, but it was functionally equivalent to the helper function. llvm-svn: 283364
* fix documentation comments; NFCSanjay Patel2016-10-051-45/+5
| | | | llvm-svn: 283361
* Allow the caller to pass in the hash.Rafael Espindola2016-10-051-2/+2
| | | | | | | If the caller already has the hash we don't have to compute it. This will be used in lld. llvm-svn: 283359
* Improve DEBUG_VALUE assembly comments for spilled bitpiecesReid Kleckner2016-10-051-7/+7
| | | | | | | | Previously we would give up when we saw the bitpiece DWARF expression and print "[complex expression]" when actually we handled bitpiece expressions outside the loop. llvm-svn: 283355
* [LV] Add helper function for predicated block probability (NFC)Matthew Simpson2016-10-051-13/+25
| | | | | | | | | | | | The cost model has to estimate the probability of executing predicated blocks. However, we currently always assume predicated blocks have a 50% chance of executing (this value is hardcoded in several places throughout the code). Since we always use the same value, this patch adds a helper function for getting this uniform probability. The function simplifies some comments and makes our assumptions more clear. In the future, we may want to extend this with actual block probability information if it's available. llvm-svn: 283354
* [mips][ias] fix li macro when values are negated with ~Simon Dardis2016-10-052-6/+34
| | | | | | | | | | | | | | | The integrated assembler evaluates the expressions such as ~0x80000000 to 0xffffffff7fffffff early in the parsing process. This patch adds compatibility with gas so that li loads the expected value (0x7fffffff) in those cases. This only occurs iff all the upper 32bits are set and maintains existing checks by not truncating the result down to 32 bits if any of the the upper bits are not set. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23399 llvm-svn: 283353
* [LV] Add isScalarWithPredication helper function (NFC)Matthew Simpson2016-10-051-11/+23
| | | | | | | | | This patch adds a single helper function for checking if an instruction will be scalarized with predication. Such instructions include conditional stores and instructions that may divide by zero. Existing checks have been updated to use the new function. llvm-svn: 283350
* Revert "[asan] LLVM: Switch to using dynamic shadow offset on iOS"Anna Zaks2016-10-051-3/+2
| | | | | | | | This reverts commit abe77a118615cd90b0d7f127e4797096afa2b394. Revert as these changes broke a Chromium buildbot. llvm-svn: 283348
* [DAG] Teach computeKnownBits and ComputeNumSignBits in SelectionDAG to look ↵Bjorn Pettersson2016-10-051-0/+34
| | | | | | | | | | | | | | | | | through EXTRACT_VECTOR_ELT. Summary: Both computeKnownBits and ComputeNumSignBits can now do a simple look-through of EXTRACT_VECTOR_ELT. It will compute the result based on the known bits (or known sign bits) for the vector that the element is extracted from. Reviewers: bogner, tstellarAMD, mkuper Subscribers: wdng, RKSimon, jyknight, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D25007 llvm-svn: 283347
* Don't pass null to memcpy. Should fix the asan bots.Rafael Espindola2016-10-051-1/+2
| | | | llvm-svn: 283336
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-057-19/+43
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert r282920 "X86: Allow conditional tail calls in Win64 "leaf" functions ↵Hans Wennborg2016-10-052-6/+6
| | | | | | | | | (PR26302)" This is suspected to cause a miscompile in Chromium. Reverting while investigating. llvm-svn: 283329
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-058-77/+25
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [X86] Don't randomly encode %rip where illegalDouglas Katzman2016-10-052-4/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D25112 llvm-svn: 283326
* [Thumb] Don't try and emit LDRH/LDRB from the constant poolJames Molloy2016-10-051-0/+1
| | | | | | | | This is not a valid encoding - these instructions cannot do PC-relative addressing. The underlying problem here is of whitelist in ARMISelDAGToDAG that unwraps ARMISD::Wrappers during addressing-mode selection. This didn't realise TargetConstantPool was actually possible, so didn't handle it. llvm-svn: 283323
* Test commit permissionOren Ben Simhon2016-10-051-2/+2
| | | | llvm-svn: 283318
* [AVR] Don't select 'MOVW' instructions when they are not supportedDylan McKay2016-10-051-15/+41
| | | | | | | We have a subtarget feature which we were ignoring, which was causing us to generate unsupported instructions for some older chips. llvm-svn: 283317
* [AVR] Add AVRRegisterInfo::splitReg functionDylan McKay2016-10-052-2/+14
| | | | | | | No tests are included just yet - this is used from the pseudo instruction expander pass, which hasn't been pulled in-tree yet. llvm-svn: 283316
* Fix machine operand traversal in ScheduleDAGInstrs::fixupKillsKrzysztof Parzyszek2016-10-051-2/+7
| | | | llvm-svn: 283315
* [AVR] Update return type of dynamic alloca passDylan McKay2016-10-051-2/+2
| | | | | | It was recently changed from 'const char*' to StringRef llvm-svn: 283312
* [AVR] Add the AVR frame lowering codeDylan McKay2016-10-052-0/+538
| | | | | | | | | | | | Summary: This allows AVR to lower frames into assembly code. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25032 llvm-svn: 283311
* [AVR] Split all of the AVR device definitions into a separate fileDylan McKay2016-10-052-487/+493
| | | | | | | We have ~500 lines of subtarget feature definitions, they don't belong in our main TableGen file. llvm-svn: 283310
* [AVR] Enable the instruction printer in the target definitionDylan McKay2016-10-051-5/+5
| | | | llvm-svn: 283309
* [AVR] Add definitions for the ATTiny102 and ATtiny104 chipsDylan McKay2016-10-051-0/+2
| | | | llvm-svn: 283308
* Re-commit "Use StringRef in Support/Darf APIs (NFC)"Mehdi Amini2016-10-0510-92/+108
| | | | | | | This reverts commit r283285 and re-commit r283275 with a fix for format("%s", Str); where Str is a StringRef. llvm-svn: 283298
* [AVR] Add the machine code backendDylan McKay2016-10-053-0/+552
| | | | | | | | | | | | | | Summary: This adds the AVR machine code backend (`AVRAsmBackend.cpp`). This will allow us to generate machine code from assembled AVR instructions. Reviewers: arsenm, kparzysz Subscribers: modocache, japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25029 llvm-svn: 283297
* [Support][CommandLine] Add cl::getRegisteredSubcommands()Dean Michael Berris2016-10-051-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | This should allow users of the library to get a range to iterate through all the subcommands that are registered to the global parser. This allows users to define subcommands in libraries that self-register to have dispatch done at a different stage (like main). It allows for writing code like the following: for (auto *S : cl::getRegisteredSubcommands()) { if (*S) { // Dispatch on S->getName(). } } This change also contains tests that show this usage pattern. Reviewers: zturner, dblaikie, echristo Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24489 llvm-svn: 283296
* Blind attempt to fix windows build after r283290 - Use StringRef in ↵Mehdi Amini2016-10-051-1/+1
| | | | | | StringSaver API (NFC) llvm-svn: 283294
* Use StringRef in ARMConstantPool APIs (NFC)Mehdi Amini2016-10-053-16/+15
| | | | llvm-svn: 283293
* Revert "Codegen: Tail-duplicate during placement."Kyle Butt2016-10-053-326/+41
| | | | | | | | | | This reverts commit 062ace9764953e9769142c1099281a345f9b6bdc. Issue with loop info and block removal revealed by polly. I have a fix for this issue already in another patch, I'll re-roll this together with that fix, and a test case. llvm-svn: 283292
* Use StringRef in FastISel API (NFC)Mehdi Amini2016-10-051-1/+1
| | | | llvm-svn: 283291
* Use StringRef in StringSaver API (NFC)Mehdi Amini2016-10-052-7/+7
| | | | llvm-svn: 283290
* Use StringRef in ARCRuntimeEntryPoints APIs (NFC)Mehdi Amini2016-10-051-6/+3
| | | | llvm-svn: 283288
OpenPOWER on IntegriCloud