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* [WinEHPrepare] Don't rely on the order of IRDavid Majnemer2015-04-102-6/+14
| | | | | | | | | | The IPToState table must be emitted after we have generated labels for all functions in the table. Don't rely on the order of the list of globals. Instead, utilize WinEHFuncInfo to tell us how many catch handlers we expect to outline. Once we know we've visited all the catch handlers, emit the cppxdata. llvm-svn: 234566
* [PowerPC] Don't crash on PPC32 i64 fp_to_uint on modern coresHal Finkel2015-04-101-0/+1
| | | | | | | | | | When we have an instruction for this (and, thus, don't generate a runtime call), we need to custom type legalize this (in a trivial way, just as we do for fp_to_sint). Fixes PR23173. llvm-svn: 234561
* [AArch64] Promote f16 operations to f32.Ahmed Bougacha2015-04-102-11/+102
| | | | | | | | | | | | | | | | | | | | For the most common ones (such as fadd), we already did the promotion. Do the same thing for all the others. Currently, we'll just crash/assert on all these operations, as there's no hardware or libcall support whatsoever. f16 (half) is specified as an interchange - not arithmetic - format, and is expected to be promoted to single-precision for arithmetic operations. While there, teach the legalizer about promoting some of the (mostly floating-point) operations that we never needed before. Differential Revision: http://reviews.llvm.org/D8648 See related discussion on the thread for: http://reviews.llvm.org/D8755 llvm-svn: 234550
* Add LLVM support for remaining integer divide and permute instructions from ↵Nemanja Ivanovic2015-04-096-52/+133
| | | | | | | | | | | ISA 2.06 This is the patch corresponding to review: http://reviews.llvm.org/D8406 It adds some missing instructions from ISA 2.06 to the PPC back end. llvm-svn: 234546
* Simplify use of formatted_raw_ostream.Rafael Espindola2015-04-096-31/+30
| | | | | | | | | | | | | | | formatted_raw_ostream is a wrapper over another stream to add column and line number tracking. It is used only for asm printing. This patch moves the its creation down to where we know we are printing assembly. This has the following advantages: * Simpler lifetime management: std::unique_ptr * We don't compute column and line number of object files :-) llvm-svn: 234535
* [CodeGen] Combine concat_vector of trunc'd scalar to scalar_to_vector.Ahmed Bougacha2015-04-091-3/+13
| | | | | | | | | | | | | | We already do: concat_vectors(scalar, undef) -> scalar_to_vector(scalar) When the scalar is legal. When it's not, but is a truncated legal scalar, we can also do: concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar) Which is equivalent, since the upper lanes are undef anyway. While there, teach the combine to look at more than 2 operands. Differential Revision: http://reviews.llvm.org/D8883 llvm-svn: 234530
* [AArch64][FastISel] Fix integer extend optimization.Juergen Ributzka2015-04-091-5/+6
| | | | | | | | | | | | | | The integer extend optimization tries to fold the extend into the load instruction. This requires us to identify if the extend has already been emitted or not and act accordingly on it. The check that was originally performed for this was not sufficient. Besides checking the ValueMap for a mapped register we also need to check if the virtual register has already an associated machine instruction that defines it. This fixes rdar://problem/20470788. llvm-svn: 234529
* Remove duplicated code and consolidate initializers.Eric Christopher2015-04-092-15/+5
| | | | llvm-svn: 234525
* clang-format bits of code to make a followup patch easy to read.Rafael Espindola2015-04-0911-26/+16
| | | | llvm-svn: 234519
* Revert "Refactoring and enhancement to FMA combine."Rafael Espindola2015-04-091-361/+172
| | | | | | This reverts commit r234513. It was failing on the bots. llvm-svn: 234518
* Define a function with "... llvm::func...".Rafael Espindola2015-04-091-6/+5
| | | | | | | | | | | | Using this instead of namespace llvm { func... } Has the advantage that the build fails with a compiler error if it gets out of sync with the .h file. llvm-svn: 234515
* Refactoring and enhancement to FMA combine.Olivier Sallenave2015-04-091-172/+361
| | | | llvm-svn: 234513
* IR: Preserve use-list order by default in bitcodeDuncan P. N. Exon Smith2015-04-091-3/+3
| | | | | | | Pull the `-preserve-*-use-list-order` flags out of "experimental" mode, and preserve use-list order by default when serializing to bitcode. llvm-svn: 234510
* Use a raw_svector_ostream instead of a raw_string_ostream.Rafael Espindola2015-04-091-6/+8
| | | | | | It saves a bit of copying. llvm-svn: 234507
* Don't repeat name in comment. NFC.Rafael Espindola2015-04-094-24/+22
| | | | llvm-svn: 234506
* Misc cleanup. NFC.Rafael Espindola2015-04-092-7/+7
| | | | | | These were lost when I reverted the raw_ostream changes. llvm-svn: 234504
* This reverts commit r234460 and r234461.Rafael Espindola2015-04-097-22/+26
| | | | | | | | | Revert "Add classof implementations to the raw_ostream classes." Revert "Use the cast machinery to remove dummy uses of formatted_raw_ostream." The underlying issue can be fixed without classof. llvm-svn: 234495
* [ARM] support for Cortex-R4/R4FJaved Absar2015-04-092-1/+19
| | | | | | | | | Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
* Nothing inherits from the asm streamer.Rafael Espindola2015-04-091-3/+1
| | | | | | Make that explicit and remove protected: llvm-svn: 234484
* [mips] Refactor saved-registers bitmask creation in ↵Toma Tabacu2015-04-091-20/+11
| | | | | | | | | | | | | | | | | | | MipsAsmPrinter::printSavedRegsBitmask. NFC. Summary: Make the code more readable by fusing the for-loops together and explicitly checking for each register class. Also, this version is more straightforward because it doesn't assume that FPU registers always come before CPU registers in the CalleeSavedInfo vector. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8033 llvm-svn: 234475
* [AArch64] Add support for dynamic stack alignmentKristof Beyls2015-04-094-43/+172
| | | | | | Differential Revision: http://reviews.llvm.org/D8876 llvm-svn: 234471
* [AArch64] Remove redundant -march option. Also fix a think-o from r234462.Lang Hames2015-04-091-1/+1
| | | | llvm-svn: 234467
* [AArch64] Teach AArch64TargetLowering::getOptimalMemOpType to consider alignmentLang Hames2015-04-091-1/+11
| | | | | | | | | | | | | restrictions when choosing a type for small-memcpy inlining in SelectionDAGBuilder. This ensures that the loads and stores output for the memcpy won't be further expanded during legalization, which would cause the total number of instructions for the memcpy to exceed (often significantly) the inlining thresholds. <rdar://problem/17829180> llvm-svn: 234462
* Use the cast machinery to remove dummy uses of formatted_raw_ostream.Rafael Espindola2015-04-095-19/+15
| | | | | | | If we know we are producing an object, we don't need to wrap the stream in a formatted_raw_ostream anymore. llvm-svn: 234461
* Add classof implementations to the raw_ostream classes.Rafael Espindola2015-04-092-7/+7
| | | | | | More uses to follow in a another patch. llvm-svn: 234460
* [LTO] do not run internalize pass from compileOptimized.Manman Ren2015-04-081-3/+0
| | | | | | | | | The input to compileOptimized is already optimized and internalized, so remove internalize pass from compileOptimized. rdar://20227235 llvm-svn: 234446
* Formmatting correctionAndrew Kaylor2015-04-081-1/+2
| | | | llvm-svn: 234438
* [WinEH] Minor bug fixes.Andrew Kaylor2015-04-081-2/+3
| | | | | | | Fixed insert point for allocas created for demoted values. Clear the nested landing pad list after it has been processed. llvm-svn: 234433
* [DAGCombine] Fix a bug in MergeConsecutiveStores.Akira Hatanaka2015-04-081-20/+21
| | | | | | | | | | | | | | | | | | | | | The bug manifests when there are two loads and two stores chained as follows in a DAG, (ld v3f32) -> (st f32) -> (ld v3f32) -> (st f32) and the stores' values are extracted from the preceding vector loads. MergeConsecutiveStores would replace the first store in the chain with the merged vector store, which would create a cycle between the merged store node and the last load node that appears in the chain. This commits fixes the bug by replacing the last store in the chain instead. rdar://problem/20275084 Differential Revision: http://reviews.llvm.org/D8849 llvm-svn: 234430
* Remove unused variable.Rafael Espindola2015-04-081-2/+0
| | | | llvm-svn: 234426
* Eliminate O(n^2) worst-case behavior in SSA constructionCameron Zwarich2015-04-081-3/+6
| | | | | | | | | The code uses a priority queue and a worklist, which share the same visited set, but the visited set is only updated when inserting into the priority queue. Instead, switch to using separate visited sets for the priority queue and worklist. llvm-svn: 234425
* [LoopAccesses] Allow analysis to complete in the presence of uniform storesAdam Nemet2015-04-082-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Re-apply r234361 with a fix and a testcase for PR23157) Both run-time pointer checking and the dependence analysis are capable of dealing with uniform addresses. I.e. it's really just an orthogonal property of the loop that the analysis computes. Run-time pointer checking will only try to reason about SCEVAddRec pointers or else gives up. If the uniform pointer turns out the be a SCEVAddRec in an outer loop, the run-time checks generated will be correct (start and end bounds would be equal). In case of the dependence analysis, we work again with SCEVs. When compared against a loop-dependent address of the same underlying object, the difference of the two SCEVs won't be constant. This will result in returning an Unknown dependence for the pair. When compared against another uniform access, the difference would be constant and we should return the right type of dependence (forward/backward/etc). The changes also adds support to query this property of the loop and modify the vectorizer to use this. Patch by Ashutosh Nema! llvm-svn: 234424
* [ARM] make vminnm/vmaxnm work with ?le, ?ge and no-nans-fp-mathScott Douglass2015-04-081-9/+18
| | | | | | | | | | Because -menable-no-nans causes fcmp conditions to be rewritten without 'o' or 'u' the recognition code in needs to cope. Also extended it to handle 'le' and 'ge. Differential Revision: http://reviews.llvm.org/D8725 llvm-svn: 234421
* [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.Toma Tabacu2015-04-081-6/+8
| | | | | | | | | | | | | | | | | | Summary: Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8"). We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8055 llvm-svn: 234406
* [jitlistener] Remove unused codeBenjamin Kramer2015-04-083-73/+0
| | | | llvm-svn: 234404
* [mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions.Toma Tabacu2015-04-081-0/+4
| | | | | | | | | | | | | | | | | Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
* Write the section header in the end.Rafael Espindola2015-04-081-27/+4
| | | | | | | | One could make the argument for writing it immediately after the ELF header, but writing it in the middle of the sections like we were doing just makes it harder for no reason. llvm-svn: 234400
* [ARM][Debug Info] Restore emitting of .cfi_def_cfa_offset for functions ↵Sergey Dmitrouk2015-04-081-1/+2
| | | | | | | | | | | | | | | | without stack frame Summary: Looks like new code from [[ http://reviews.llvm.org/rL222057 | rL222057 ]] doesn't account for early `return` in `ARMFrameLowering::emitPrologue`, which leads to loosing `.cfi_def_cfa_offset` directive for functions without stack frame. Reviewers: echristo, rengolin, asl, t.p.northover Reviewed By: t.p.northover Subscribers: llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8606 llvm-svn: 234399
* [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic.Toma Tabacu2015-04-081-4/+2
| | | | | | | | | | | | | | | | Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
* [MachineLICM] Cleanup, remove unused parameters. NFC.Daniel Jasper2015-04-081-13/+7
| | | | llvm-svn: 234392
* [InstCombine] Refactor out OptimizeOverflowCheck. NFCI.Sanjoy Das2015-04-083-100/+172
| | | | | | | | | | | | | | | | | | | Summary: This patch adds an enum `OverflowCheckFlavor` and a function `OptimizeOverflowCheck`. This will allow InstCombine to optimize overflow checks without directly introducing an intermediate call to the `llvm.$op.with.overflow` instrinsics. This specific change is a refactoring and does not intend to change behavior. Reviewers: majnemer, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8888 llvm-svn: 234388
* Revert "[LoopAccesses] Allow analysis to complete in the presence of uniform ↵Adam Nemet2015-04-082-16/+11
| | | | | | | | | | stores" This reverts commit r234361. It caused PR23157. llvm-svn: 234387
* [bpf] support BPF backend as shared libraryAlexei Starovoitov2015-04-081-1/+1
| | | | | | | | | dependencies were not set correctly for shared library build. static was ok Patch by Brenden Blanco. llvm-svn: 234386
* Oops, didn't mean to commit my debug fprintfsMatthias Braun2015-04-081-4/+1
| | | | llvm-svn: 234385
* R600/SI: Add some missing overridesTom Stellard2015-04-082-2/+2
| | | | llvm-svn: 234384
* LiveInterval: Fix computeFromMainRange() producing adjacent segments with ↵Matthias Braun2015-04-081-14/+45
| | | | | | | | | | | | | | | same valno If two livesegments from different subranges happened to have the same definition they could possibly end up as two adjacent segments in the main liverange with the same value number which is not allowed. Detect such cases and fix them in the 2nd pass of computeFromMainRange() if necessary. No testcase as there is only an out-of-tree target where I can sensibly come up with one. llvm-svn: 234382
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-0814-133/+1369
| | | | | | | | | | | | | This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
* R600/SI: Add missing SOPK instructionsTom Stellard2015-04-083-13/+72
| | | | llvm-svn: 234380
* R600/SI: Don't print offset0/offset1 DS operands when they are 0Tom Stellard2015-04-081-4/+8
| | | | llvm-svn: 234379
* ELFObjectWriter.cpp: Prune obsolete \param since r234342. [-Wdocumentation]NAKAMURA Takumi2015-04-081-1/+0
| | | | llvm-svn: 234377
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