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* Add support for generating a call graph profile from Branch Frequency Info.Michael J. Spencer2018-06-276-7/+172
| | | | | | | | | | | | | | | | | | | | | === Generating the CG Profile === The CGProfile module pass simply gets the block profile count for each BB and scans for call instructions. For each call instruction it adds an edge from the current function to the called function with the current BB block profile count as the weight. After scanning all the functions, it generates an appending module flag containing the data. The format looks like: ``` !llvm.module.flags = !{!0} !0 = !{i32 5, !"CG Profile", !1} !1 = !{!2, !3, !4} ; List of edges !2 = !{void ()* @a, void ()* @b, i64 32} ; Edge from a to b with a weight of 32 !3 = !{void (i1)* @freq, void ()* @a, i64 11} !4 = !{void (i1)* @freq, void ()* @b, i64 20} ``` Differential Revision: https://reviews.llvm.org/D48105 llvm-svn: 335794
* Move some code from PDBFileBuilder to MSFBuilder.Zachary Turner2018-06-272-73/+91
| | | | | | | | The code to emit the pieces of the MSF file were actually in PDBFileBuilder. Move this to MSFBuilder so that we can theoretically emit an MSF without having a PDB file. llvm-svn: 335789
* [X86] Make folding table checking threadsafeBenjamin Kramer2018-06-271-4/+3
| | | | | | | This is a benign race, but tsan likes to complain about it. Just make it happy. llvm-svn: 335788
* [X86] In X86DAGToDAGISel::PreprocessISelDAG, make sure we don't access N ↵Craig Topper2018-06-271-0/+1
| | | | | | | | | | after we delete it. If we turn X86ISD::AND into ISD::AND, we delete N. But we were continuing onto the next block of code even though N no longer existed. Just happened to notice it. I assume asan didn't notice it because we explicitly unpoison deleted nodes and give them a DELETE_NODE opcode. llvm-svn: 335787
* [RISCV] Add machine function pass to merge base + offsetSameer AbuAsal2018-06-275-208/+296
| | | | | | | | | | | | | | | | | | | | | | | | Summary: In r333455 we added a peephole to fix the corner cases that result from separating base + offset lowering of global address.The peephole didn't handle some of the cases because it only has a basic block view instead of a function level view. This patch replaces that logic with a machine function pass. In addition to handling the original cases it handles uses of the global address across blocks in function and folding an offset from LW\SW instruction. This pass won't run for OptNone compilation, so there will be a negative impact overall vs the old approach at O0. Reviewers: asb, apazos, mgrang Reviewed By: asb Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones Differential Revision: https://reviews.llvm.org/D47857 llvm-svn: 335786
* [DAGCombine] Disable TokenFactor simplifications when optnone.Nirav Dave2018-06-271-0/+4
| | | | llvm-svn: 335773
* [X86] Fix unmatched parenthesis in r335768Fangrui Song2018-06-271-1/+1
| | | | llvm-svn: 335769
* [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the ↵Craig Topper2018-06-271-5/+20
| | | | | | | | | | SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. The %eiz/%riz are dummy registers that force the encoder to emit a SIB byte when it normally wouldn't. By emitting them in the disassembly output we ensure that assembling the disassembler output would also produce a SIB byte. This should match the behavior of objdump from binutils. llvm-svn: 335768
* [globalisel][legalizer] Add AtomicOrdering to LegalityQuery and use it in ↵Daniel Sanders2018-06-273-8/+18
| | | | | | | | | | | | | AArch64 Now that we have the ability to legalize based on MMO's. Add support for legalizing based on AtomicOrdering and use it to correct the legalization of the atomic instructions. Also extend all() to be a variadic template as this ruleset now requires 3 and 4 argument versions. llvm-svn: 335767
* [DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zerosSanjay Patel2018-06-271-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As noted in the D44909 review, the transform from (fptosi+sitofp) to ftrunc can produce -0.0 where the original code does not: #include <stdio.h> int main(int argc) { float x; x = -0.8 * argc; printf("%f\n", (float)((int)x)); return 0; } $ clang -O0 -mavx fp.c ; ./a.out 0.000000 $ clang -O1 -mavx fp.c ; ./a.out -0.000000 Ideally, we'd use IR/node flags to predicate the transform, but the IR parser doesn't currently allow fast-math-flags on the cast instructions. So for now, just use the function attribute that corresponds to clang's "-fno-signed-zeros" option. Differential Revision: https://reviews.llvm.org/D48085 llvm-svn: 335761
* [ThinLTO] Print names in function import debug messages when availableTeresa Johnson2018-06-271-8/+15
| | | | | | | | | | | | | | | | Summary: Rather than just print the GUID, when it is available in the index, print the global name as well in the function import thin link debug messages. Names will be available when the combined index is being built by the same process, e.g. a linker or "llvm-lto2 run". Reviewers: davidxl Subscribers: mehdi_amini, inglorion, eraman, steven_wu, llvm-commits Differential Revision: https://reviews.llvm.org/D48612 llvm-svn: 335760
* [MachineOutliner] Don't outline sequences where x16/x17/nzcv are live acrossJessica Paquette2018-06-273-28/+41
| | | | | | | | | | | | | | It isn't safe to outline sequences of instructions where x16/x17/nzcv live across the sequence. This teaches the outliner to check whether or not a specific canidate has x16/x17/nzcv live across it and discard the candidate in the case that that is true. https://bugs.llvm.org/show_bug.cgi?id=37573 https://reviews.llvm.org/D47655 llvm-svn: 335758
* [X86] Use bts/btr/btc for single bit set/clear/complement of a variable bit ↵Craig Topper2018-06-271-0/+31
| | | | | | | | | | position If we are just modifying a single bit at a variable bit position we can use the BT* instructions to make the change instead of shifting a 1(or rotating a -1) and doing a binop. These instruction also ignore the upper bits of their index input so we can also remove an and if one is present on the index. Fixes PR37938. llvm-svn: 335754
* [AliasSet] Fix UnknownInstructions printingJakub Kuderski2018-06-271-2/+6
| | | | | | | | | | | | | | | | | Summary: AliasSet::print uses `I->printAsOperand` to print UnknownInstructions. The problem is that not all UnknownInstructions have names (e.g. call instructions). When such instructions are printed, they appear as `<badref>` in AliasSets, which is very confusing, as the values are perfectly valid. This patch fixes that by printing UnknownInstructions without a name using `print` instead of `printAsOperand`. Reviewers: asbirlea, chandlerc, sanjoy, grosser Reviewed By: asbirlea Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48609 llvm-svn: 335751
* [X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics ↵Craig Topper2018-06-273-131/+83
| | | | | | | | that don't take a mask as input to exclude '.mask.' from their name. I think the intrinsics named 'avx512.mask.' should refer to the previous behavior of taking a mask argument in the intrinsic instead of using a 'select' or 'and' instruction in IR to accomplish the masking. This is more consistent with the goal that eventually we will have no intrinsics that have masking builtin. When we reach that goal, we should have no intrinsics named "avx512.mask". llvm-svn: 335744
* [AMDGPU] Convert rcp to rcp_iflagStanislav Mekhanoshin2018-06-276-12/+45
| | | | | | | | | | | If a source of rcp instruction is a result of any conversion from an integer convert it into rcp_iflag instruction. No FP exception can ever happen except division by zero if a single precision rcp argument is a representation of an integral number. Differential Revision: https://reviews.llvm.org/D48569 llvm-svn: 335742
* [AArch64] Reverting FP16 vcvth_n_s64_f16 to fixLuke Geeson2018-06-271-2/+0
| | | | llvm-svn: 335737
* [AArch64] Add custom lowering for v4i8 trunc storeAdhemerval Zanella2018-06-273-8/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a custom trunc store lowering for v4i8 vector types. Since there is not v.4b register, the v4i8 is promoted to v4i16 (v.4h) and default action for v4i8 is to extract each element and issue 4 byte stores. A better strategy would be to extended the promoted v4i16 to v8i16 (with undef elements) and extract and store the word lane which represents the v4i8 subvectores. The construction: define void @foo(<4 x i16> %x, i8* nocapture %p) { %0 = trunc <4 x i16> %x to <4 x i8> %1 = bitcast i8* %p to <4 x i8>* store <4 x i8> %0, <4 x i8>* %1, align 4, !tbaa !2 ret void } Can be optimized from: umov w8, v0.h[3] umov w9, v0.h[2] umov w10, v0.h[1] umov w11, v0.h[0] strb w8, [x0, #3] strb w9, [x0, #2] strb w10, [x0, #1] strb w11, [x0] ret To: xtn v0.8b, v0.8h str s0, [x0] ret The patch also adjust the memory cost for autovectorization, so the C code: void foo (const int *src, int width, unsigned char *dst) { for (int i = 0; i < width; i++) *dst++ = *src++; } can be vectorized to: .LBB0_4: // %vector.body // =>This Inner Loop Header: Depth=1 ldr q0, [x0], #16 subs x12, x12, #4 // =4 xtn v0.4h, v0.4s xtn v0.8b, v0.8h st1 { v0.s }[0], [x2], #4 b.ne .LBB0_4 Instead of byte operations. llvm-svn: 335735
* [NEON] Support vldNq intrinsics in AArch32 (LLVM part)Ivan A. Kosarev2018-06-275-70/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the q versions of the dup (load-to-all-lanes) NEON intrinsics, such as vld2q_dup_f16() for example. Currently, non-q versions of the dup intrinsics are implemented in clang by generating IR that first loads the elements of the structure into the first lane with the lane (to-single-lane) intrinsics, and then propagating it other lanes. There are at least two problems with this approach. First, there are no double-spaced to-single-lane byte-element instructions. For example, there is no such instruction as 'vld2.8 { d0[0], d2[0] }, [r0]'. That means we cannot rely on the to-single-lane intrinsics and instructions to implement the q versions of the dup intrinsics. Note that to-all-lanes instructions do support all sizes of data items, including bytes. The second problem with the current approach is that we need a separate vdup instruction to propagate the structure to each lane. So for vld4q_dup_f16() we would need four vdup instructions in addition to the initial vld instruction. This patch introduces dup LLVM intrinsics and reworks handling of the currently supported (non-q) NEON dup intrinsics to expand them into those LLVM intrinsics, thus eliminating the need for using to-single-lane intrinsics and instructions. Additionally, this patch adds support for u64 and s64 dup NEON intrinsics. These are marked as Arch64-only in the ARM NEON Reference, but it seems there are no reasons to not support them in AArch32 mode. Please correct, if that is wrong. That's what we generate with this patch applied: vld2q_dup_f16: vld2.16 {d0[], d2[]}, [r0] vld2.16 {d1[], d3[]}, [r0] vld3q_dup_f16: vld3.16 {d0[], d2[], d4[]}, [r0] vld3.16 {d1[], d3[], d5[]}, [r0] vld4q_dup_f16: vld4.16 {d0[], d2[], d4[], d6[]}, [r0] vld4.16 {d1[], d3[], d5[], d7[]}, [r0] Differential Revision: https://reviews.llvm.org/D48439 llvm-svn: 335733
* [DAGCombiner] visitSDIV - add special case handling for (sdiv X, 1) -> X in ↵Simon Pilgrim2018-06-271-11/+7
| | | | | | | | pow2 expansion For divisor = 1, perform a select of X - reduces scalarisation of simple SDIVs llvm-svn: 335727
* [DAGCombiner] visitSDIV - simplify pow2 handling. NFCI.Simon Pilgrim2018-06-271-29/+12
| | | | | | Use the builtin constant folding of getNode() etc. instead of doing it manually. llvm-svn: 335720
* [DAGCombiner] Fold SDIV(%X, MIN_SIGNED) -> SELECT(%X == MIN_SIGNED, 1, 0)Simon Pilgrim2018-06-271-0/+5
| | | | | | Fixes PR37569. llvm-svn: 335719
* [DAGCombiner] Don't accept signbit sdiv divisors in sdiv-by-pow2 vector ↵Simon Pilgrim2018-06-271-0/+2
| | | | | | expansion (PR37569) llvm-svn: 335717
* [AArch64] Remove Duplicate FP16 Patterns with same encoding, match on ↵Luke Geeson2018-06-274-35/+54
| | | | | | existing patterns llvm-svn: 335715
* AMDGPU/NFC: Fix typo in commentKonstantin Zhuravlyov2018-06-271-1/+1
| | | | llvm-svn: 335707
* [InstCombine] Avoid creating mis-sized dbg.values in commonCastTransforms()Vedant Kumar2018-06-271-2/+5
| | | | | | | | | | | | | | This prevents InstCombine from creating mis-sized dbg.values when replacing a sequence of casts with a simpler cast. For example, in: (fptrunc (floor (fpext X))) -> (floorf X) We no longer emit dbg.value(X) (with a 32-bit float operand) to describe (fpext X) (which is a 64-bit float). This was diagnosed by the debugify check added in r335682. llvm-svn: 335696
* [X86] Don't store register and memory FMA3 opcodes in the same ↵Craig Topper2018-06-273-99/+30
| | | | | | | | | | X86InstrFMA3Group. Nothing was using this relationship. By splitting them we no longer need to worry about register or memory entries being empty in a group. The memory folding tables in X86InstrInfo.cpp can be used to access this relationship if needed. llvm-svn: 335694
* Revert "[asan] Instrument comdat globals on COFF targets"Evgeniy Stepanov2018-06-261-33/+8
| | | | | | Causes false positive ODR violation reports on __llvm_profile_raw_version. llvm-svn: 335681
* [ORC] Don't call isa<> on a null value.Lang Hames2018-06-261-1/+1
| | | | | | This should fix the recent builder failures in the test-global-ctors.ll testcase. llvm-svn: 335680
* [ORC] Fix a missing return value.Lang Hames2018-06-261-0/+2
| | | | llvm-svn: 335677
* [JumpThreading] Don't try to rewrite a use if it's already valid.Michael Zolotukhin2018-06-261-10/+12
| | | | | | | | | | | | | | | | | | | Summary: When recording uses we need to rewrite after cloning a loop we need to check if the use is not dominated by the original def. The initial assumption was that the cloned basic block will introduce a new path and thus the original def will only dominate the use if they are in the same BB, but as the reproducer from PR37745 shows it's not always the case. This fixes PR37745. Reviewers: haicheng, Ka-Ka Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48111 llvm-svn: 335675
* [ORC] Add a dependence on MC to LLVMBuild.txtLang Hames2018-06-261-2/+2
| | | | llvm-svn: 335673
* [ORC] Add LLJIT and LLLazyJIT, and replace OrcLazyJIT in LLI with LLLazyJIT.Lang Hames2018-06-267-19/+402
| | | | | | | | | | | | | | | | | | | LLJIT is a prefabricated ORC based JIT class that is meant to be the go-to replacement for MCJIT. Unlike OrcMCJITReplacement (which will continue to be supported) it is not API or bug-for-bug compatible, but targets the same use cases: Simple, non-lazy compilation and execution of LLVM IR. LLLazyJIT extends LLJIT with support for function-at-a-time lazy compilation, similar to what was provided by LLVM's original (now long deprecated) JIT APIs. This commit also contains some simple utility classes (CtorDtorRunner2, LocalCXXRuntimeOverrides2, JITTargetMachineBuilder) to support LLJIT and LLLazyJIT. Both of these classes are works in progress. Feedback from JIT clients is very welcome! llvm-svn: 335670
* AMDGPU: Silence unused warnings in waitcnt insertion pass in release buildKonstantin Zhuravlyov2018-06-261-1/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D48607 llvm-svn: 335669
* [X86][AsmParser] Recommit r335658Jessica Paquette2018-06-261-0/+8
| | | | | | | Recommit of r335658 so that it does not change the behaviour of any existing error output. llvm-svn: 335668
* Rename skipDebugInfo -> skipDebugIntrinsics, NFCVedant Kumar2018-06-261-1/+1
| | | | | | | | | | | | | This addresses post-commit feedback about the name 'skipDebugInfo' being misleading. This name could be interpreted as meaning 'a function that skips instructions with debug locations'. The new name, 'skipDebugIntrinsics', makes it clear that this function only skips debug info intrinsics. Thanks to Adrian Prantl for pointing this out! llvm-svn: 335667
* [ORC] Reset AsynchronousSymbolQuery's NotifySymbolsResolved callback on error.Lang Hames2018-06-261-3/+4
| | | | | | | | AsynchronousSymbolQuery::canStillFail checks the value of the callback to prevent sending it redundant error notifications, so we need to reset it after running it. llvm-svn: 335664
* [ORC] Move the VSOList typedef out of VSO.Lang Hames2018-06-261-3/+2
| | | | llvm-svn: 335663
* [ORC] Fix a FIXME by moving MangleAndInterner to Core.h.Lang Hames2018-06-262-12/+14
| | | | llvm-svn: 335661
* Revert "[X86][AsmParser] Emit an error when RIP-relative instructions are ↵Jessica Paquette2018-06-261-7/+0
| | | | | | | | | | used in 32-bit mode" This reverts commit 4850a9aae8b38c7deadc103d634ec7397e6c323b. It caused MC/X86/x86_errors.s to fail. Will fix and recommit shortly. llvm-svn: 335660
* [X86][AsmParser] Emit an error when RIP-relative instructions are used in ↵Jessica Paquette2018-06-261-0/+7
| | | | | | | | | | | | | 32-bit mode Right now, when we use RIP-relative instructions in 32-bit mode, we'll just assert and crash. This adds an error message which tells the user that they can't do that in 32-bit mode, so that we don't crash (and also can see the issue outside of assert builds). llvm-svn: 335658
* [AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsicStanislav Mekhanoshin2018-06-261-0/+3
| | | | | | | | This intrinsic selects v_mad_f32 regardless of fp32 denorm support. Differential Revision: https://reviews.llvm.org/D48573 llvm-svn: 335654
* [DAGCombiner] use isBitwiseNot to simplify code; NFCSanjay Patel2018-06-261-8/+3
| | | | llvm-svn: 335652
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-264-0/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces most argument uses with loads, but for now not all. The code in SelectionDAG for calling convention lowering is actively harmful for amdgpu_kernel. It attempts to split the argument types into register legal types, which results in low quality code for arbitary types. Since all kernel arguments are passed in memory, we just want the raw types. I've tried a couple of methods of mitigating this in SelectionDAG, but it's easier to just bypass this problem alltogether. It's possible to hack around the problem in the initial lowering, but the real problem is the DAG then expects to be able to use CopyToReg/CopyFromReg for uses of the arguments outside the block. Exposing the argument loads in the IR also has the advantage that the LoadStoreVectorizer can merge them. I'm not sure the best approach to dealing with the IR argument list is. The patch as-is just leaves the IR arguments in place, so all the existing code will still compute the same kernarg size and pointlessly lowers the arguments. Arguably the frontend should emit kernels with an empty argument list in the first place. Alternatively a dummy array could be inserted as a single argument just to reserve space. This does have some disadvantages. Local pointer kernel arguments can no longer have AssertZext placed on them as the equivalent !range metadata is not valid on pointer typed loads. This is mostly bad for SI which needs to know about the known bits in order to use the DS instruction offset, so in this case this is not done. More importantly, this skips noalias arguments since this pass does not yet convert this to the equivalent !alias.scope and !noalias metadata. Producing this metadata correctly seems to be tricky, although this logically is the same as inlining into a function which doesn't exist. Additionally, exposing these loads to the vectorizer may result in degraded aliasing information if a pointer load is merged with another argument load. I'm also not entirely sure this is preserving the current clover ABI, although I would greatly prefer if it would stop widening arguments and match the HSA ABI. As-is I think it is extending < 4-byte arguments to 4-bytes but doesn't align them to 4-bytes. llvm-svn: 335650
* ConstantFold: Don't fold global address vs. null for addrspace != 0Matt Arsenault2018-06-261-3/+6
| | | | | | | | | | | Not sure why this logic seems to be repeated in 2 different places, one called by the other. On AMDGPU addrspace(3) globals start allocating at 0, so these checks will be incorrect (not that real code actually tries to compare these addresses) llvm-svn: 335649
* Use a variable to appease a no-asserts bot, NFCVedant Kumar2018-06-261-0/+1
| | | | | | | Failure URL: http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/22836 llvm-svn: 335648
* [ConstantRange] Add support of mul in makeGuaranteedNoWrapRegion.Tim Shen2018-06-261-0/+58
| | | | | | | | | | | | Summary: This is trying to add support for r334428. Reviewers: sanjoy Subscribers: jlebar, hiraditya, bixia, llvm-commits Differential Revision: https://reviews.llvm.org/D48399 llvm-svn: 335646
* LoopUnroll: Allow analyzing intrinsic call costsMatt Arsenault2018-06-261-2/+7
| | | | | | | | | | | I'm not sure why the code here is skipping calls since TTI does try to do something for general calls, but it at least should allow intrinsics. Skip intrinsics that should not be omitted as calls, which is by far the most common case on AMDGPU. llvm-svn: 335645
* [Local] Add a convenient insertReplacementDbgValues overload, NFCVedant Kumar2018-06-262-8/+14
| | | | | | | Add an overload for the common case where the replacement dbg.values have the same DIExpressions as the originals. llvm-svn: 335643
* [Local] Sink salvageDI's early exit into helper functions, NFCVedant Kumar2018-06-261-5/+12
| | | | | | | | salvageDebugInfo() performs a check that allows it to exit early without doing a DenseMap lookup. It's a bit neater and marginally more useful to sink this early exit into the findDbg{Addr,Users,Values} helpers. llvm-svn: 335642
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