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* Add definition of WSBH (Word Swap Bytes within Halfwords), which is anAkira Hatanaka2011-12-202-8/+10
| | | | | | | | | | instruction supported by mips32r2, and add a pattern which replaces bswap with a ROTR and WSBH pair. WSBW is removed since it is not an instruction the current architectures support. llvm-svn: 147015
* 64-bit uint-fp conversion nodes are expanded.Akira Hatanaka2011-12-201-0/+2
| | | | llvm-svn: 147014
* Enable custom lowering DYNAMIC_STACKALLOC nodes.Akira Hatanaka2011-12-201-0/+1
| | | | llvm-svn: 147013
* Set the correct stack pointer register that should be saved or restored.Akira Hatanaka2011-12-201-1/+1
| | | | llvm-svn: 147012
* Fix a nasty bug in the type remapping stuff that I added that is breaking ↵Chris Lattner2011-12-201-1/+8
| | | | | | | | | | | | | | | | kc++ on the build bot in some cases. The basic issue happens when a source module contains both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if the destination module contains a "%foo" type, and it will return true... because both the source and destination modules are in the same LLVMContext. We don't want to map source types to other source types, so don't do the remapping if the mapped type came from the source module. Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is pretty great that way. llvm-svn: 147010
* ARM .req register name aliases are case insensitive, just like regnames.Jim Grosbach2011-12-201-3/+4
| | | | llvm-svn: 147009
* Add function MipsDAGToDAGISel::SelectMULT and factor out code that generatesAkira Hatanaka2011-12-201-37/+47
| | | | | | | nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. llvm-svn: 147008
* Fix indentation.Akira Hatanaka2011-12-201-115/+115
| | | | llvm-svn: 147007
* 64-bit data directive.Akira Hatanaka2011-12-201-1/+1
| | | | llvm-svn: 147005
* 32-to-64-bit sext_inreg pattern.Akira Hatanaka2011-12-201-0/+5
| | | | llvm-svn: 147004
* Add 64-bit extload patterns.Akira Hatanaka2011-12-201-2/+12
| | | | llvm-svn: 147003
* Add patterns for matching extloads with 64-bit address. The patterns are enabledAkira Hatanaka2011-12-201-5/+13
| | | | | | only when the target ABI is N64. llvm-svn: 147001
* Move comment to appropriate place.Jim Grosbach2011-12-201-1/+1
| | | | llvm-svn: 147000
* Add code in MipsDAGToDAGISel for selecting constant +0.0.Akira Hatanaka2011-12-201-0/+6
| | | | | | MIPS64 can generate constant +0.0 with a single DMTC1 instruction. llvm-svn: 146999
* Heed spill slot alignment on ARM.Jakob Stoklund Olesen2011-12-202-3/+4
| | | | | | | | | | | Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. llvm-svn: 146997
* Revert part of r146995 that was accidentally commmitted.Akira Hatanaka2011-12-201-6/+0
| | | | llvm-svn: 146996
* 32-to-64-bit sign extension pattern.Akira Hatanaka2011-12-202-0/+8
| | | | llvm-svn: 146995
* Add a pattern for matching zero-store with 64-bit address. The pattern is ↵Akira Hatanaka2011-12-201-1/+4
| | | | | | | | enabled only when the target ABI is N64. llvm-svn: 146992
* ARM assembly parsing and encoding for VST2 single-element, double spaced.Jim Grosbach2011-12-202-37/+129
| | | | llvm-svn: 146990
* Fix assert condition.Lang Hames2011-12-201-1/+1
| | | | llvm-svn: 146987
* Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak2011-12-206-10/+21
| | | | llvm-svn: 146986
* Add support to add named metadata operand.Devang Patel2011-12-201-0/+11
| | | | | | Patch by Andrew Wilkins! llvm-svn: 146984
* ARM assembly parsing and encoding for VLD2 single-element, double spaced.Jim Grosbach2011-12-202-43/+171
| | | | llvm-svn: 146983
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-207-78/+79
| | | | llvm-svn: 146981
* First steps in ARM AsmParser support for .eabi_attribute and .archJason W Kim2011-12-201-0/+18
| | | | | | | (Both used for Linux gnueabi) No behavioral change yet (no tests need so far) llvm-svn: 146977
* This is the second fix related to VZEXT_MOVL node.Elena Demikhovsky2011-12-201-1/+6
| | | | | | | | | | | | | | | | | | | | The failure that I see in the current version is: LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14] 0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13] 0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12] 0x18b9870: v4i64 = undef [ID=4] 0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10] 0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9970: i32 = Constant<0> [ID=3] 0x18b9170: v2i64 = undef [ORD=1] [ID=1] 0x18b9570: i32 = Constant<2> [ID=5] llvm-svn: 146975
* Begin teaching the X86 target how to efficiently codegen patterns thatChandler Carruth2011-12-202-6/+17
| | | | | | | | | | | | | | | use the zero-undefined variants of CTTZ and CTLZ. These are just simple patterns for now, there is more to be done to make real world code using these constructs be optimized and codegen'ed properly on X86. The existing tests are spiffed up to check that we no longer generate unnecessary cmov instructions, and that we generate the very important 'xor' to transform bsr which counts the index of the most significant one bit to the number of leading (most significant) zero bits. Also they now check that when the variant with defined zero result is used, the cmov is still produced. llvm-svn: 146974
* Fixes a potential compilation error.Manuel Klimek2011-12-201-12/+0
| | | | | | | Pulling the template implementation into the header to guarantee that it's visible to all possible instantiations. llvm-svn: 146973
* Pulls the implementation of skip() into JSONParser.Manuel Klimek2011-12-201-11/+24
| | | | | | | This is the first step towards migrating more of the parser implementation into the parser class. llvm-svn: 146971
* Addressing style issues in JSON parser.Manuel Klimek2011-12-201-4/+2
| | | | llvm-svn: 146968
* Fix up the CMake build for the new files added in r146960, they'reChandler Carruth2011-12-2015-0/+16
| | | | | | likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
* Unweaken vtables as per ↵David Blaikie2011-12-20105-20/+518
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* LSR: Fix another corner case in expansion of postinc users.Andrew Trick2011-12-201-0/+14
| | | | | | Fixes PR11571: Instruction does not dominate all uses llvm-svn: 146950
* Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson2011-12-201-2/+5
| | | | | | | | | | | | We used to rely on the *eh_sjlj_setjmp instructions to mark that a function with setjmp/longjmp exception handling clobbers all the registers. But with the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are expanded away earlier, before PEI can see them to determine what registers to save and restore. Mark the dispatchsetup instruction in the same way, since that instruction cannot be expanded early. This also more accurately reflects when the registers are clobbered. llvm-svn: 146949
* ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach2011-12-201-0/+17
| | | | | | | | | | "mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 llvm-svn: 146937
* Now that PR11464 is fixed, reapply the patch to fix PR11464, Chris Lattner2011-12-201-0/+25
| | | | | | | | merging types by name when we can. We still don't guarantee type name linkage but we do it when obviously the right thing to do. This makes LTO type names easier to read, for example. llvm-svn: 146932
* fix PR11464 by preventing the linker from mapping two different struct types ↵Chris Lattner2011-12-201-12/+27
| | | | | | from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. llvm-svn: 146929
* Add basic generic CodeGen support for half.Dan Gohman2011-12-204-17/+46
| | | | llvm-svn: 146927
* ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.Jim Grosbach2011-12-192-0/+45
| | | | | | | | e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117" rdar://10603913 llvm-svn: 146925
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-195-3/+72
| | | | | | rdar://9932658 llvm-svn: 146921
* Add a if-conversion optimization that allows 'true' side of a diamond to beEvan Cheng2011-12-191-5/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 llvm-svn: 146914
* Add patterns for matching immediates whose lower 16-bit is cleared. TheseAkira Hatanaka2011-12-192-0/+10
| | | | | | patterns emit a single LUi instruction instead of a pair of LUi and ORi. llvm-svn: 146900
* Attempt to fix PR11607 by shuffling around which class defines which methods.Eli Friedman2011-12-191-5/+5
| | | | llvm-svn: 146897
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-1910-132/+117
| | | | llvm-svn: 146896
* ARM NEON two-operand aliases for VPADD.Jim Grosbach2011-12-191-0/+10
| | | | | | rdar://10602276 llvm-svn: 146895
* Remove definitions of double word shift plus 32 instructions. Assembler orAkira Hatanaka2011-12-191-21/+9
| | | | | | | direct-object emitter should emit the appropriate shift instruction depending on the shift amount. llvm-svn: 146893
* ARM VFP pre-UAL mnemonic aliases for fmul[sd].Jim Grosbach2011-12-192-1/+4
| | | | llvm-svn: 146892
* Remove unused predicate.Akira Hatanaka2011-12-191-3/+0
| | | | llvm-svn: 146889
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-191-3/+1
| | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) llvm-svn: 146888
* ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].Jim Grosbach2011-12-192-1/+5
| | | | llvm-svn: 146887
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